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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1556 条记录，以下是251-260 订阅

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On leveraging approximations for exact system-level design space exploration: work-in-progress 18

On leveraging approximations for exact system-level design s...

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proceedings of the international conference on hardware/software codesign and system synthesis

作者： Kai Neubauer Christian Haubelt Philipp Wanko Torsten Schaub University of Rostock Germany University of Potsdam Germany

ISBN: (纸本)9781538655627

In order to find good design points for embedded systems, an efficient exploration of the design space is imperative. The ever-increasing complexity of embedded systems, however, results in a deterioration of the overall exploration performance. The DSE essentially consists of two parts: (1) the search for feasible solutions and (2) the evaluation of found feasible solutions. While the search has been massively improved by ASPmT-based strategies, the evaluation emerges as the main bottleneck. Tragically, evaluating bad solutions takes as much time as evaluating good ones. Hence, in this paper we study the utilization of approximations in the evaluation process integrated in an ASPmT-based DSE to identify bad solutions more quickly while still retaining the exact Pareto-front.

关键词： system-level design approximation design space exploration

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Advancing remote attestation via computer-aided formal verification of designs and synthesis of executables: opinion 19

Advancing remote attestation via computer-aided formal verif...

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proceedings of the 12th conference on Security and Privacy in Wireless and Mobile Networks

作者： Karim Eldefrawy Gene Tsudik SRI International UC Irvine

ISBN: (纸本)9781450367264

Remote Attestation (RA) of embedded/smart/IoT devices is a very important issue on today's security landscape. RA enables a verifier to measures the current internal memory state of an untrusted remote device (prover). RA helps the verifier establish a static or dynamic root of trust in prover. Despite much prior work, state-of-the-art RA techniques unfortunately still lack any solid foundation and offer no ironclad security, safety or robustness guarantees. This paper argues that computer-aided formal verification, and synthesis of executables, of RA protocols and hybrid (software-hardware) architectures is required and currently unaddressed. We believe that this is achievable with current (computer-aided) formal methods frameworks and tools, and that this can help advance and mature RA research if used to establish more rigorous and clear security arguments. To support our opinion, we highlight several examples where subtle issues were missed in the design and security analysis of RA techniques. Despite deceptive simplicity of such protocols, manual analyses and ad hoc implementations often lead to over-simplification of (and subsequent glossing over) important details in the underlying processor and system architectures. Computer-aided formal verification forces a more scrupulous and disciplined consideration of such details, since, otherwise, verification simply fails. The key objective of the research direction we propose is to increase confidence in correctness and security guarantees of current and future RA techniques and their implementations.

关键词： secure remote attestation formal verification formal methods

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Towards software performance estimation based on register-transfer level descriptions

Towards software performance estimation based on register-tr...

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2017 IEEE Nordic Circuits and systems conference, NORCAS 2017: NORCHIP and international Symposium of system-on-Chip, SoC 2017

作者： Puttnies, Henning Niemann, Christoph Rohde, Sascha Timmermann, Dirk Schacht, Jorg University of Rostock Applied Microelectronics and Computer Engineering Rostock18051 Germany Max Planck Institute of Plasma Physics Wendelsteinstrae 1 Greifswald Germany

ISBN: (纸本)9781538628447

The concept of hardware-software codesign allows to cope with the increasing complexity of very large scale integration (VLSI) systems. This concept is based on design space exploration (DSE), which means the systematic altering of design parameters (e.g., parallelization, serialisation, implementation of a functionality in software or hardware) to improve the final design. Existing DSE approaches work with high-level descriptions (e.g., systemC) of the functionality. However, if existing systems (or submodules of those) shall be reused, only a synthesizable register-transfer level (RTL) description of these functionalities is necessarily given. Consequently, the RTL modules cannot be considered during the DSE. We propose an approach to this problem of reasonable practical relevance. To conduct the DSE, we estimate the software execution time of a functionality based on its RTL description. We show in an evaluation that this estimation is possible based on RTL code. In addition, we propose several suggestions to mitigate the problem that the software execution time of a functionality is highly dependent on the input data, which are often unknown at design time. © 2017 IEEE.

关键词： hardware-software codesign

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HW/SW Co-design Experimental Framework using Configurable SoCs

HW/SW Co-design Experimental Framework using Configurable So...

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international conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Xu, Siyuan Chen, Jianqi Schafer, Benjamin Carrion Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75083 USA

ISBN: (纸本)9781538637975

This paper presents an open source HW/SW co-design experimental platform based on behavioral benchmarks mapped onto a programmable SoC using High-Level synthesis. HW/SW co-design has become extremely relevant in today's VLSI design processes. Due to the unstoppable increase in transistor count of integrated circuits (ICs), most ICs are currently heterogenous SoCs containing micro-processors, memories, interfaces and dedicated hardware accelerators. This has lead FPGA vendors to introduce programmable/configurable SoCs (CSoC), e.g. Altera's Cyclone/Arria/Stratix SoCs and Xilinx's Zynq family. At the same time, newer design methodologies are required to increase the design productivity like HLS. The main problem is that there are no benchmarks that can be directly mapped onto these CSoC using HLS to conduct research in HW/SW co-design as well as to teach HW/SW co-design. A HW/SW co-design experimental framework is presented here to bridge this gap. A set of synthesizable systemC designs have been created and ported onto a Cyclone V SoC FPGA. The designs have been created in such a way that they can be fully executed on the embedded processor or accelerated by mapping the most computationally intensive kernel onto the reconfigurable fabric. A software layer allows the creation of different HW/SW configurations by allowing tasks to be executed on the embedded processor or mapped as hardware accelerator on the reconfigurable logic. The complete environment is open source and available online. A running time and energy comparison between the benchmarks mapped onto a desktop PC processor in ANSI-C and systemC, an embedded ARM processor and the ARM+FPGA version are presented showing that the accelerated benchmarks do only lead to speed-ups compared to the embedded processor's version when the system's communication part (sending and receiving data) is lower than 50% of the total runtime. We believe that this open source HW/SW design platform is a good starting point to enco

关键词： embedded systems field programmable gate arrays hardware-software codesign system-on-chip VLSI Field programmable gate arrays Co-design hardware/software co-design system-on-chip Very large scale integration Embedded systems hue lightness saturation embedded processor hardware accelerator BENCHMARKS SYNTHETIC ORGANIC CHEMICALS open source

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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

2014 International Conference on Hardware/Software Codesign ...

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2014 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2014

ISBN: (纸本)9781450330510

The proceedings contain 35 papers. The topics discussed include: HEFT: a hybrid system-level framework for enabling energy-efficient fault-tolerance in NoC based MPSoCs;an efficient technique for computing importance measures in automatic design of dependable embedded systems;towards scalable symbolic routing for multi-objective networked embedded system design and optimization;hardware/software co-design for a wireless sensor network platform;a PCM translation layer for integrated memory and storage management;leveraging microarchitectural side channel information to efficiently enhance program control flow integrity;saving energy without defying deadlines on mobile GPU-based heterogeneous systems;prediction and control of bursty cloud workloads: a fractal framework;TSP: thermal safe power - efficient power budgeting for many-core systems in dark silicon;and flattening-based mapping of imperfect loop nests for CGRA.

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Adaptive Iterative Improvement GP-based Methodology for HW/SW Co-synthesis of Embedded systems 7

Adaptive Iterative Improvement GP-based Methodology for HW/S...

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7th international Joint conference on Pervasive and Embedded Computing and Communication systems (PECCS)

作者： Gorski, Adam Ogorzalek, Maciej Jagiellonian Univ Cracow Dept Informat Technol Prof Stanislawa Lojasiewicza 11 Krakow Poland

ISBN: (纸本)9789897582660

The paper presents a novel adaptive genetic programming based iterative improvement algorithm for hardware/software co-synthesis of distributed embedded systems. The algorithm builds solutions by starting from suboptimal architecture (the fastest) and using system-building options improves the system's quality. Most known genetic programming algorithms for co-synthesis of embedded systems are built choosing fixed probability. In our approach we decided to change the probability during the work of the program.

关键词： Embedded systems Architecture hardware/software Co-synthesis Genetic Programming Genetic Algorithm Adaptive systems

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Design Space Exploration for a hardware-accelerated Embedded Real-Time Pose Estimation using Vivado HLS

Design Space Exploration for a Hardware-accelerated Embedded...

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international conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Joseph, Jan Moritz Mey, Morten Ehlers, Kristian Blochwitz, Christopher Winker, Tobias Pionteck, Thilo Otto Von Guericke Univ Inst Informat & Kommunikat Tech D-39106 Magdeburg Germany Univ Lubeck Inst Tech Informat D-23562 Lubeck Germany

ISBN: (纸本)9781538637975

This paper presents a design space exploration for a hardware/software co-design of a pose estimation algorithm targeting embedded systems. To fulfill resource and performance constraints, the design space is gradually explored. First, the performance is optimized in multiple steps and then, second, the resource utilization is reduced using Vivado HLS. Plus, data transport overhead of different protocols is evaluated since in this application latency is more relevant than throughput. In addition, the hardware accelerators are integrated into a software system. As hardware platform a Xilinx Zynq FPGA with a ARM dual core A-9 is used. A speedup of 2-2.5 in comparison to an optimized software solution is achieved while efficiently using the small FPGA's resources enabling pose estimation on embedded systems with 30 fps.

关键词： high level synthesis hardware acceleration embedded systems design space exploration pose estimation

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Driving Self - Learning system Based on the Virtual Reality 3

Driving Self - Learning System Based on the Virtual Reality

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3rd IEEE international conference on Computer and Communications (ICCC)

作者： Sun, Daowei Liu, Xianzhong East China Normal Univ Sch Comp Sci & Software Engn Shanghai Peoples R China MoE Software Hardware Codesign Engn Res Ctr Shanghai Peoples R China

ISBN: (纸本)9781509063529

Nowadays, with the continuous improvement of people's living standards, people's demand for cars has been growing, which also leads to more and more people learn to drive. But there arc many problems behind this phenomenon. For example, too long waiting time, low-quality coaches, lack of spare time, high test cost, and low pass rate. The paper mainly proposes a Driving self-learning system based on the virtual reality, which is used to solve the problems on above. This application runs in the form of a Unity executable file on PC and uses the Oculus Rift as a head mounted virtual display and a force feedback steering wheel as the controller. The application is aimed at new drivers who have little or no experience driving a car but can be used by experienced drivers who wish to improve their driving

关键词： recommendation self-learning virtual driving unity3D C#

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Embedded system-on-Chip Design of Atrial Fibrillation Classifier 14

Embedded System-on-Chip Design of Atrial Fibrillation Classi...

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international SoC Design conference (ISOCC)

作者： Lim, Huey Woan Hau, Yuan Wen Othman, Mohd Afzan Lim, Chiao Wen Univ Teknol Malaysia Fac Biosci & Med Engn IJN UTM Cardiovasc Engn Ctr Johor Baharu Malaysia Univ Teknol Malaysia Fac Elect Engn Dept Elect & Comp Engn Johor Baharu Malaysia Univ Teknol MARA Fac Med Sungai Buloh Selangor Malaysia

ISBN: (纸本)9781538622858

Atrial Fibrillation (AFIB) is one of the major risk factors of stroke and heart failure which can be observed from the electrocardiogram (ECG). This paper presents an embedded system-on-chip (SoC) architecture design of AFIB detection based on stationary wavelet transform (SWT) and artificial neural network (ANN) algorithm for heart screening propose. The architecture is designed using the hardware/software codesign technique and prototyped on Altera DE2-115 FPGA platform. hardware acceleration of compute intensive FFT operation is also carried out to enhance computation timing performance. The whole system consumes 40,830 LEs of Altera Cyclone-IV FPGA device. The total computation time of AFIB classifier is 22 seconds for 10 seconds ECG input data with the accuracy of 95.3% which able to detect AFIB rhythm, normal sinus rhythm, and non-AFIB rhythm.

关键词： Atrial fibrillation (AFIB) artificial neural network (ANN) FPGA system-on-chip (SoC) wavelet transform

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Build Fast, Trade Fast: FPGA-based High-Frequency Trading using High-Level synthesis

Build Fast, Trade Fast: FPGA-based High-Frequency Trading us...

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international conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Boutros, Andrew Grady, Brett Abbas, Mustafa Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781538637975

High-Frequency Trading (HFT) systems require extremely low latency in response to market updates. This motivates the use of Field-Programmable Gate Arrays (FPGAs) to accelerate different system components such as the network stack, financial protocol parsing, order book handling and even custom trading algorithms. However, the long cycle of developing and verifying FPGA designs makes it challenging for HFT software developers to deploy such highly-dynamic systems, especially with their limited hardware design expertise. We present a complete highly-optimized infrastructure that implements low-latency system components in C++ using High-Level synthesis (HLS). We also develop a framework that enables HFT algorithm developers to implement their trading algorithms in a high-level programming language and rapidly integrate it to the rest of the system. We implemented our HLS-based system on a Xilinx Kintex Ultrascale FPGA running at 156 MHz. Our on-board measurements show an end-to-end round-trip latency less than 870ns, which is comparable to that achieved by prior RTL-based implementations but requires reduced system development time and effort.

关键词： Algorithm design and analysis Protocols hardware Field programmable gate arrays software algorithms IP networks Switches

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