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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1554 条记录，以下是261-270 订阅

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FingerVoice: A Syllable Based Input system via Fingers Touching 17

FingerVoice: A Syllable Based Input System via Fingers Touch...

引用

19th international ACM SIGACCESS conference on Computers and Accessibility (ASSETS)

作者： Chen, Wenjie Ma, Yangyang Chai, Zhilei Chen, Mingsong East China Normal Univ MoE Engn Res Ctr Software Hardware Codesign Shanghai Peoples R China State Key Lab Math Engn & Adv Comp Wuxi Jiangsu Peoples R China Jiangnan Univ Sch IoT Engn Wuxi Jiangsu Peoples R China

ISBN: (纸本)9781450349260

This paper proposes a novel input system via fingers touching, called FingerVoice. Instead of traditional letter based input system, it is based on syllables. Fingers on the left hand stand for consonants while fingers on the right hand for vowels. Fingers from both hands touch each other to form a syllable. We use a pair of gloves with conductive finger caps to detect the touch. As an example, the implementation of Chinese is presented in details. By connecting it to a smart phone via Bluetooth, a utility speaking system is implemented to help the speech-impaired to "speak" via smart phone. Our experimental result shows that this syllable based input device is faster than letter based input devices.

关键词： input device fingervoice speech impaired syllable gloves

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FPGA-Accelerated for Constrained High Dispersal Network 15

FPGA-Accelerated for Constrained High Dispersal Network

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15th IEEE international Symposium on Parallel and Distributed Processing with Applications (ISPA) / 16th IEEE international conference on Ubiquitous Computing and Communications (IUCC)

作者： Chen, Yanliang Zhu, Minghua Xiao, Bo Meng, Dan East China Normal Univ MOE Res Ctr Software Hardware Codesign Engn & App Shanghai Peoples R China

ISBN: (纸本)9781538637906

In recent years, the Deep Neural Network (DNN) has been successfully used in image classification. Most of existing DNN often need to learn a very large set of parameters, which require a huge amount of computational resources and time to train these model parameters using the gradient descent and back-propagation procedure. To solve this issue, the PCANet has been developed for high efficient design and training of the DNN. Compared with traditional DNN, PCANet has simpler structure and better performance, which makes it attractive for hardware design. To overcome the limitations of PCANet and significantly improve its performance, we have proposed a novel model named Constrained High Dispersal Network (CHDNet) which is a variant of PCANet. In this paper, we implement the CHDNet on the Xilinx ZYNQ FPGA to ensure the instantaneity of the system with lower power than personal computer needed by taking advantage of the algorithmic parallelism and ZYNQ architecture. Our experimental results over two major datasets, the MNIST dataset for handwritten digits recognition, and the Extended Yale B dataset for face recognition, demonstrate that our model of implementation on FPGA is more than 15x faster than software implementation on PC (Intel i7-4720HQ, 2.6GHz).

关键词： Image classification Deep neural network FPGA High-level synthesis

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Synthesizable Assertion in hardware and software Development 2017

Synthesizable Assertion in Hardware and Software Development

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proceedings of the international conference on Imaging, Signal Processing and Communication

作者： Ooi Ruey Hock Zulfiqar Ali Bin Abd.Aziz J-Wing Teh University Sains Malaysia Intel Corporation(M) Sdn.Bhd.

ISBN: (纸本)9781450352895

Assertion Based Validation(ABV) is an approach in which the design intent is captured in an executable form where all the out of range and missing intent intents will trigger an error which indicates the fall-outs. By using these assertions can enable early detection of very basic software and hardware bugs in the design. system Verilog is a hardware description language that combine with verification and commonly used as assertion language with its powerful assertion function embedded in the language itself. However not all system verilog language can be synthesize into hardware component and because of the limitation, it only use in software simulation phase of a design cycle. The approach to enable the ABV module in system verilog format to be synthesized into a portion of the hardware is the intent of this paper. It defines the synthesizable building blocks of the assertion modules. This can utilized by both hardware and software development in pre-silicon stage through reconfigurable hardware or Field Programmable Gate Array(FPGA). In hardware debug, the synthesized assertions will point to the area of failure, reducing the scope of debug. In software development, the synthesized assertions will point to invalid configurations of hardware registers. The assertions will be synthesized into a separate hardware block which is programmed into a reconfigurable hardware or FPGA together with the Design-Under-Test(DUT). The assertion validation hardware block consists of a ‘Detection and Distribution' block and a series of ‘Property Tracking' block to track the multiple events separately. If all separate events are met but the expected scenario is not met, a register bit will be set for this assertion point to signify failure. Final assertion results will be written to memory on the reconfigurable hardware or FGPA. The purpose of this paper is to identify the common assertion function that widely use in hardware design and synthesis of these assertion properties from

关键词： Assertion Based Validation, ABV system Verilog Field Programmable Gate Array FPGA

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Sound design for a system of 1000 distributed independent audio-visual devices

Sound design for a system of 1000 distributed independent au...

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international conference on New Interfaces for Musical Expression, NIME 2017

作者： Ferguson, Sam Rowe, Anthony Bown, Oliver Birtles, Liam Bennewith, Chris Creativity & Cognition Studios Faculty of Engineering & IT University of Technology Sydney Australia *** Australia Interactive Media Laboratory UNSW Art and Design Australia Bournemouth University Australia School of Art Design & Architecture Plymouth University United Kingdom

This paper describes the sound design for Bloom, a light and sound installation made up of 1000 distributed independent audio-visual pixel devices, each with RGB LEDs, Wifi, Accelerometer, GPS sensor, and sound hardware. These types of systems have been explored previously, but only a few systems have exceeded 30-50 devices and very few have included sound capability, and therefore the sound design possibilities for large systems of distributed audio devices are not well understood. In this article we describe the hardware and software implementation of sound synthesis for this system, and the implications for design of media for this context. © 2017 Steering Committee of the international conference on New Interfaces for Musical Expression. All rights reserved.

关键词： Internet of things

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INFORMATION RICH MAPPING REQUIREMENT TO PRODUCT ARCHITECTURE THROUGH FUNCTIONAL system DEPLOYMENT: THE MULTI ENTITY DOMAIN APPROACH 21

INFORMATION RICH MAPPING REQUIREMENT TO PRODUCT ARCHITECTURE...

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21st international conference on Engineering Design (ICED)

作者： Hauksdottir, Dagny Mortensen, Niels Henrik Tech Univ Denmark Lyngby Denmark

ISBN: (纸本)9781904670940

Successful transformation of design information from customer requirements to design implementation is critical for engineering design. As systems become complex the tracking of how customer requirements are implement becomes difficult. Existing approaches suggest so called domain modelling for mapping requirements to architecture. These approaches do not fully support the steps and information created during product design synthesis. Design Specifications used to guide the design are often documented in text based documents, outside the design models. This results in lack of traceability which may impede the ability to evolve, maintain or reuse systems. In this paper the Multi Entity Domain Approach (MEDA) is presented. The approach combines different design information within the domain views, incorporates both software and hardware design and supports iterative requirements definition. The results suggest that it is possible to present design information in structural domain views, presenting more elaborate information of the design synthesis than provided by previous approaches. However, further validation in a practical project setting is required to validate the approach.

关键词： Design specifications Domain engineering systems Engineering (SE) Requirements Knowledge management

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Efficient virtual memory sharing via on-accelerator page table walking in heterogeneous embedded SoCs

Efficient virtual memory sharing via on-accelerator page tab...

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ACM Transactions on Embedded Computing systems

作者： Vogel, Pirmin Kurth, Andreas Weinbuch, Johannes Marongiu, Andrea Benini, Luca Integrated Systems Laboratory ETH Zurich Gloriastrasse 35 Zurich8092 Switzerland Electrical Electronic and Information Engineering Department University of Bologna Viale Risorgimento 2 Bologna40126 Italy

Shared virtual memory is key in heterogeneous systems on chip (SoCs) that combine a general-purpose host processor with a many-core accelerator, both for programmability and performance. In contrast to the fullblown, hardware-only solutions predominant in modern high-end systems, lightweight hardware-software co-designs are better suited in the context of more power- and area-constrained embedded systems and provide additional benefits in terms of flexibility and predictability. As a downside, the latter solutions require the host to handle in software synchronization in case of page misses as well as miss handling. This may incur considerable run-time overheads. In this work, we present a novel hardware-software virtual memory management approach for many-core accelerators in heterogeneous embedded SoCs. It exploits an accelerator-side helper thread concept that enables the accelerator tomanage its virtualmemory hardware autonomously while operating cache-coherently on the page tables of the user-space processes of the host. This greatly reduces overhead with respect to host-side solutions while retaining flexibility. We have validated the design with a set of parameterizable benchmarks and real-world applications covering various application domains. For purely memory-bound kernels, the accelerator performance improves by a factor of 3.8 compared with host-based management and lies within 50% of a lower-bound ideal memory management unit. © 2017 ACM.

关键词： Memory management units Acceleration Benchmarking Computer operating systems Embedded systems hardware hardware software codesign Linux Physical addresses system on chip Heterogeneous systems High end systems Many core accelerators Novel hardware Programmability Shared virtual memory Virtual memory Virtual memory management

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Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress 17

Heterogeneous redundancy to address performance and cost in ...

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proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： M. Naghashi S. H. Mozafari S. Hessabi Sharif University of Technology Tehran Iran McGill University Montreal Canada

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their specification in the first place: yie... 详细信息

ISBN: (纸本)9781450351850

关键词： system-level design redundancy manufacturability

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Towards the application of flask security architecture to SoC design: work-in-progress 17

Towards the application of flask security architecture to So...

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proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Festus Hategekimana Christophe Bobda University of Arkansas

ISBN: (纸本)9781450351850

In this work, we explore a security reference monitor (RM) design which borrows from the Flask security architecture. Our RM design goal is to achieve complete mediation by checking and verifying the authority and the authenticity of every access to every system object in systems-on-chip (SoCs). Access decisions are administered by a security logic "server" implemented as an extension of the peripheral bus. Initial results show a minimal increase in resource overhead and no significant impact on the performance.

关键词： secure execution trojan hardware sandbox field programmable gate arrays (FPGAs) component authentication process systems-on-chip (SoC)

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Implementing geo-blocking and spoofing protection in multi-domain software defined interconnects 1

Implementing geo-blocking and spoofing protection in multi-d...

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1st international Workshop on Security and Dependability of Multi-Domain Infrastructures, XDOM0 2017

作者： Kumary, Himal Mercian, Anu Banerjee, Sujata Russell, Craig Sivaramany, Vijay UNSW Australia Hewlett-Packard Enterprise United States VMware United States CSIRO Data 61 Australia

ISBN: (纸本)9781450349376

Motivated by recent attacks like the Australian census website meltdown in 2016, this paper proposes a system for high-level specification and synthesis of intents for Geo- Blocking and IP Spoofing protection at a software Defined Interconnect. In contrast to todays methods that use expensive custom hardware and/or manual configuration, our solution allows the operator to specify high-level intents, which are automatically compiled to flow-level rules and pushed into the interconnect fabric. We define a grammar for specifying the security policies, and a compiler for converting these to connectivity rules. We prototype our system on the open-source ONOS Controller platform, demonstrate its functionality in a multi-domain SDN fabric interconnecting legacy border routers, and evaluate its performance and scalability in blocking DDoS attacks. © 2017 ACM.

关键词： software defined networking

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MEMOCODE 2017 - 15th ACM-IEEE international conference on Formal Methods and Models for system Design

MEMOCODE 2017 - 15th ACM-IEEE International Conference on Fo...

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15th ACM-IEEE international conference on Formal Methods and Models for system Design, MEMOCODE 2017

ISBN: (纸本)9781450350938

The proceedings contain 23 papers. The topics discussed include: the quest for average response time;stochastic contracts for cyber-physical system design under probabilistic requirements;on improving rare event simulation for probabilistic safety analysis;quantifying the information leak in cache attacks via symbolic execution;efficient realization of logical execution times in legacy embedded software;model-based availability analysis for automated production systems: a case study;model-based, mutation-driven test case generation via heuristic-guided branching search;automatic evaluation of complex design decisions in component-based software architectures;more than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models;property templates for checking source code security;formal verification and control synthesis of complex dynamic systems: model-based and data-driven methods;extraction of missing formal assumptions in under-constrained designs;hyperproperties of real-valued signals;using the Coq theorem prover to verify complex data structure invariants;a core calculus for secure hardware: its formal semantics and proof system;releasing VDM proof obligations with SMT solvers;and simulation of cyber-physical systems using IEC61499.

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