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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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Implementing geo-blocking and spoofing protection in multi-domain software defined interconnects 1

Implementing geo-blocking and spoofing protection in multi-d...

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1st international Workshop on Security and Dependability of Multi-Domain Infrastructures, XDOM0 2017

作者： Kumary, Himal Mercian, Anu Banerjee, Sujata Russell, Craig Sivaramany, Vijay UNSW Australia Hewlett-Packard Enterprise United States VMware United States CSIRO Data 61 Australia

ISBN: (纸本)9781450349376

Motivated by recent attacks like the Australian census website meltdown in 2016, this paper proposes a system for high-level specification and synthesis of intents for Geo- Blocking and IP Spoofing protection at a software Defined Interconnect. In contrast to todays methods that use expensive custom hardware and/or manual configuration, our solution allows the operator to specify high-level intents, which are automatically compiled to flow-level rules and pushed into the interconnect fabric. We define a grammar for specifying the security policies, and a compiler for converting these to connectivity rules. We prototype our system on the open-source ONOS Controller platform, demonstrate its functionality in a multi-domain SDN fabric interconnecting legacy border routers, and evaluate its performance and scalability in blocking DDoS attacks. © 2017 ACM.

关键词： software defined networking

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MEMOCODE 2017 - 15th ACM-IEEE international conference on Formal Methods and Models for system Design

MEMOCODE 2017 - 15th ACM-IEEE International Conference on Fo...

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15th ACM-IEEE international conference on Formal Methods and Models for system Design, MEMOCODE 2017

ISBN: (纸本)9781450350938

The proceedings contain 23 papers. The topics discussed include: the quest for average response time;stochastic contracts for cyber-physical system design under probabilistic requirements;on improving rare event simulation for probabilistic safety analysis;quantifying the information leak in cache attacks via symbolic execution;efficient realization of logical execution times in legacy embedded software;model-based availability analysis for automated production systems: a case study;model-based, mutation-driven test case generation via heuristic-guided branching search;automatic evaluation of complex design decisions in component-based software architectures;more than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models;property templates for checking source code security;formal verification and control synthesis of complex dynamic systems: model-based and data-driven methods;extraction of missing formal assumptions in under-constrained designs;hyperproperties of real-valued signals;using the Coq theorem prover to verify complex data structure invariants;a core calculus for secure hardware: its formal semantics and proof system;releasing VDM proof obligations with SMT solvers;and simulation of cyber-physical systems using IEC61499.

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An efficient hardware design for cerebellar models using approximate circuits: special session paper 17

An efficient hardware design for cerebellar models using app...

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proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Honglan Jiang Leibo Liu Jie Han University of Alberta Edmonton AB Canada Tsinghua University Beijing China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： multiplier cerebellar model approximate circuits adder

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Remote detection of unauthorized activity via spectral analysis: work-in-progress 17

Remote detection of unauthorized activity via spectral analy...

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proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Fatih Karabacak Umit Ogras Sule Ozev Arizona State University

ISBN: (纸本)9781450351850

Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enter the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operation bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.

关键词： EM emission hardware/firmware trojan detection IoT security

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Optimal Functional-Unit Assignment and Buffer Placement for Probabilistic Pipelines 16

Optimal Functional-Unit Assignment and Buffer Placement for ...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Weiwen Sha, Edwin H. -M. Zhuge, Qingfeng Chen, Xianzhang Chongqing Univ Coll Comp Sci Chongqing Peoples R China

ISBN: (纸本)9781450344838

Applications, such as streaming applications, modeled by task graphs can be efficiently executed in a pipelined fashion. In synthesizing application-specific heterogeneous pipelined systems, where to place buffers (called buffer placement) and what type of functional units to execute each task (called functional assignment) are two critical problems. In reality, the execution time of each task may not be fixed, which makes the above two problems much more challenging. In this paper, we model the execution time of each task on different types of functional units as a random variable. Our objective is to obtain the optimal functional assignment and buffer placement, such that the resultant pipeline can satisfy the timing requirement with the minimum cost under the guaranteed confidence probability. This paper presents efficient algorithms to achieve the objective. Experiments show that other techniques cannot find any feasible solutions in many cases while ours can. Even for the cases where they can find feasible solutions, our algorithms achieve the minimum cost which gives a significant reduction on the total cost, compared with existing techniques.

关键词： High-level synthesis application-specific system optimal algorithms probabilistic scenario

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Efficient Design Space Exploration by Knowledge Transfer 16

Efficient Design Space Exploration by Knowledge Transfer

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Li, Dandan Wang, Senzhang Yao, Shuzhen Liu, Yu-Hang Cheng, Yuanqi Sun, Xian-He Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China Nanjing Univ Aeronaut & Astronaut Coll Comp Sci & Technol Nanjing Jiangsu Peoples R China Collaborat Innovat Ctr Novel Software Technol & I Nanjing Jiangsu Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China IIT Dept Comp Sci Chicago IL 60616 USA

ISBN: (纸本)9781450344838

Due to the exponentially increasing size of design space of microprocessors and time-consuming simulations, predictive models have been widely employed in design space exploration (DSE). Traditional approaches mostly build a program-specific predictor that needs a large number of program-specific samples. Thus considerable simulation cost is required for each program. In this paper, we study the novel problem of transferring knowledge from the labeled samples of previous programs to help predict the responses of the new target program whose labeled samples are very sparse. Inspired by the recent advances of transfer learning, we propose a transfer learning based DSE framework TrDSE to build a more efficient and effective predictive model for the target program with only a few simulations by borrowing knowledge from previous programs. Specifically, TrDSE includes two phases: 1) clustering the programs based on the proposed orthogonal array sampling and the distribution related features, and 2) with the guidance of clustering results, predicting the responses of configurations in design space of the target program by a transfer learning based regression algorithm. We evaluate the proposed TrDSE on the benchmarks of SPEC CPU 2006 suite. The results demonstrate that the proposed framework is more efficient and effective than state-of-art DSE techniques.

关键词： Design space exploration Processor design Knowledge transfer

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Research of the on-line system for detecting metal particles in oil 13

Research of the on-line system for detecting metal particles...

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2017 13th IEEE international conference on Electronic Measurement & Instruments (ICEMI)

作者： Zuo Yunbo Gu Yuhai Key Laboratory of Modern Measurement & Control Technology (Beijing Information Science & Technology University) Ministry of Education

ISBN: (纸本)9781509050369;9781509050352

Wear is one important type of the common mechanical faults. The number and size information of wear metal particles in lubricating oil can reflect the wear fault state of mechanical equipment. Electromagnetic particle information detection is one important method of particle detection. It has the advantages of simple structure, fast response, small influence of external interference such as vibration and oil bubbles, and so on. In this paper, aiming at the difficulties of particle electromagnetic detection, the mathematical model of exciting magnetic field and induction electromotive force was analyzed. The structure of differential screw electromagnetic sensor was designed. The direct digital frequency synthesis method was used to generate the excitation signal. Based on STM32 F103 and MK60 DN512 DSP chips, the signal detection hardware system was designed. The information analysis software system was designed based on QT C++ language. The developed system can detect the minimum number of 180 mesh wear metal particles, and it can be the research condition for the analysis of mechanical equipment wear state, fault diagnosis and early fault warning.

关键词： wear fault electromagnetic particle detection exciting and induction coil

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Exploring fast and slow memories in HMP core types: work-in-progress 17

Exploring fast and slow memories in HMP core types: work-in-...

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proceedings of the Twelfth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis Companion

作者： Bryan Donyanavard Amir Mahdi Hosseini Monazzah Tiago Mück Nikil Dutt University of California Sharif University of Technology

ISBN: (纸本)9781450351850

Studies have shown memory and computational needs vary independently across applications. Recent work has explored using hybrid memory technology (SRAM+NVM) in on-chip memories of multicore processors (CMPs) to support the varied needs of diverse workloads. Such works suggest architectural modifications that require supplemental management in the memory hierarchy. Instead, we propose to deploy hybrid memory in a manner that integrates seamlessly with the existing heterogeneous multicore (HMP) architectural model, and therefore does not require any architectural modification, simply the integration of different memory technologies on-chip. We evaluate platforms with a combination of fast (SRAM cache) and slow (STT-MRAM cache) core-types for mobile workloads.

关键词： SPM scratchpad memory hardware/software memory management many-core architectures virtualization

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A novel emulation model of the cardiac conduction system

A novel emulation model of the cardiac conduction system

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作者： Andalam, Sidharta Allen, Nathan Malik, Avinash Roop, Partha S. Trew, Mark University of Auckland Private Bag 92019 Auckland1142 New Zealand

Models of the cardiac conduction system are usually at two extremes: (1) high fidelity models with excellent precision but lacking a real-time response for emulation (hardware in the loop simulation);or (2) models amenable for emulation, but that do not exhibit appropriate dynamic response, which is necessary for arrhythmia susceptibility. We introduce two abstractions to remedy the situation. The first abstraction is a new cell model, which is a semi-linear hybrid automata. The proposed model is as computationally efficient as current state-of-the-art cell models amenable for emulation. Yet, unlike these models, it is also able to capture the dynamic response of the cardiac cell like the higher-fidelity models. The second abstraction is the use of smooth-tokens to develop a new path model, connecting cells, which is efficient in terms of memory consumption. Moreover, the memory requirements of the path model can be statically bounded and are invariant to the emulation step size. Results show that the proposed semi-linear abstraction for the cell reduces the execution time by up to 44%. Furthermore, the smooth-tokens based path model reduces the memory consumption by 40 times when compared to existing path models. This paves the way for the emulation of complex cardiac conduction systems, using hardware code-generators. © 2017 ACM.

关键词： Cells

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ICENCO 2017 - 13th international Computer Engineering conference: Boundless Smart Societies

ICENCO 2017 - 13th International Computer Engineering Confer...

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13th international Computer Engineering conference, ICENCO 2017

ISBN: (纸本)9781538642665

The proceedings contain 71 papers. The topics discussed include: analysis of faults fixing system using rough sets: a case study in large-scale telecommunication company (telecom Egypt);a novel language-adaptable accent reduction software template;an economic model for cloud service composition based on user's preferences;learning the sit-to-stand human behavior: an inverse optimal control approach;performance analysis for diverse simulation scenarios for DSDV, DSR and AODV MANET routing protocols;providing QoS in contention management for software transactional memory;a data mining experimentation framework to improve Six Sigma projects;performance enhancement of free space optical (FSO) systems using polarized DWDM-OFDM technique under atmospheric disturbances;high-level synthesis hardware implementation and verification of HEVC DCT on SoC-FPGA;fuzzy logic-based clustering approach with mobile sink for WSNs;Twitter features distributions across similar labelers;energy aware ad-hoc on demand multipath distance vector (EAAOMDV);performance enhancement of free space optical (FSO) systems using polarized DWDM-OFDM technique under atmospheric disturbances;prediction of DNA methylation for every CpG loci in chromosome 18 in embryonic stem cells using support vector machine;and an energy efficient and adaptive clustering for wireless sensor network (CH-leach) using leach protocol.

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