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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1556 条记录，以下是291-300 订阅

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hardware-Accelerated Pose Estimation for Embedded systems using Vivado HLS

Hardware-Accelerated Pose Estimation for Embedded Systems us...

引用

international conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Joseph, Jan Moritz Winker, Tobias Ehlers, Kristian Blochwitz, Christopher Pionteck, Thilo Otto von Guericke Univ Inst Informat & Kommunikat Tech D-39106 Magdeburg Germany Univ Lubeck Inst Tech Informat D-23562 Lubeck Germany

ISBN: (纸本)9781509037070

The focus of this work is to facilitate pose estimation and, thus, gesture recognition for embedded systems, although these are tasks with high computational performance requirements. Therefore, an existing pose estimation algorithm is optimized for Xilinx High Level synthesis (HLS). The resulting hardware acceleration cores are compared for different optimizations and, finally, we propose a hardware/software system design for a Xilinx Zynq Zedboard. Using this method, we achieve a speedup of 1.6 in comparison to a software solution on the ARM processor and, thus, facilitate hand tracking for embedded systems with low power consumption.

关键词： pose estimation high level synthesis hardware acceleration embedded systems Xilinx Zynq Vivado HLS

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Partial FPGA Bitstream Encryption Enabling hardware DRM in Mobile Environments 16

Partial FPGA Bitstream Encryption Enabling Hardware DRM in M...

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ACM international conference on Computing Frontiers (CF)

作者： Barbareschi, Mario Cilardo, Alessandro Mazzeo, Antonino Univ Naples Federico II Dept Elect Engn & Informat Technol CeRICT Scrl Ctr Reg Informat Commun Technol Via Claudio 21 I-80125 Naples Italy

ISBN: (纸本)9781450341288

The concept of digital right management (DRM) has become extremely important in current mobile environments. This paper shows how partial bitstream encryption can allow the secure distribution of hardware applications resembling the mechanisms of traditional software DRM. Building on the recent developments towards the secure distribution of hardware cores, the paper demonstrates a prototypical implementation of a user mobile device supporting such distribution mechanisms. The prototype extends the Android operating system with support for hardware reconfigurability and showcases the interplay of novel security concepts enabled by hardware DRM, the advantages of a design flow based on high-level synthesis, and the opportunities provided by current software-rich reconfigurable systems-onChips. Relying on this prototype, we also collected extensive quantitative results demonstrating the limited overhead incurred by the secure distribution architecture.

关键词： system-on-chip

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FPGA-Based Parallel Implementation of SURF Algorithm 22

FPGA-Based Parallel Implementation of SURF Algorithm

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22nd IEEE international conference on Parallel and Distributed systems (ICPADS)

作者： Chen, Wenjie Ding, Shuaishuai Chai, Zhilei He, Daojing Zhang, Weihua Zhang, Guanhua Peng, Qiwei Luo, Wang East China Normal Univ MoE Engn Res Ctr Software Hardware Codesign Techn Shanghai 200062 Peoples R China Jiangnan Univ Sch IoT Engn Wuxi 214122 Peoples R China State Key Lab Math Engn & Adv Comp Wuxi 214125 Peoples R China Fudan Univ Parallel Proc Inst Shanghai 200433 Peoples R China NARI Grp Corp State Grid Elect Power Res Inst Nanjing 211000 Jiangsu Peoples R China

ISBN: (纸本)9781509044573

SURF (Speeded up robust features) detection is used extensively in object detection, tracking and matching. However, due to its high complexity, it is usually a challenge to perform such detection in real time on a general-purpose processor. This paper proposes a parallel computing algorithm for the fast computation of SURF, which is specially designed for FPGAs. By efficiently exploiting the advantages of the architecture of an FPGA, and by appropriately handling the inherent parallelism of the SURF computation, the proposed algorithm is able to significantly reduce the computation time. Our experimental results show that, for an image with a resolution of 640x480, the processing time for computing using SURF is only 0.047 seconds on an FPGA (XC6SLX150T, 66.7 MHz), which is 13 times faster than when performed on a typical i3-3240 CPU (with a 3.4 GHz main frequency) and 249 times faster than when performed on a traditional ARM system (CortexTM-A8, 1 GHz).

关键词： SURF FPGA parallel computing High Level synthesis

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Empowering OpenMP with Automatically Generated hardware 16

Empowering OpenMP with Automatically Generated Hardware

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international conference on Embedded Computer systems - Architectures, Modeling and Simulation (SAMOS)

作者： Podobas, Artur Brorsson, Mats Royal Inst Technol Sch Informat & Commun Technol Kistagangen 16 S-16440 Stockholm Sweden

ISBN: (纸本)9781509030767

OpenMP enables productive software development that targets shared-memory general purpose systems. However, OpenMP compilers today have little support for future heterogeneous systems - systems that will more than likely contain Field Programmable Gate Arrays (FPGAs) to compensate for the lack of parallelism available in general purpose systems. We have designed a high-level synthesis flow that automatically generates parallel hardware from unmodified OpenMP programs. The generated hardware is composed of accelerators tailored to act as hardware instances of the OpenMP task primitive. We drive decision making of complex details within accelerators through a constraint-programming model, minimizing the expected input from the (often) hardware-oblivious software developer. We evaluate our system and compare them to two state of the art architectures - the Xeon PHI and the AMD Opteron - where we find our accelerators to perform on par with the two ASIC processors.

关键词： Decision making

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On-the-fly computing: Self-aware heterogeneous multi-cores

On-the-fly computing: Self-aware heterogeneous multi-cores

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Marco Platzner Paderborn University Paderborn Germany

ISBN: (纸本)9781509035908

In this article, we briefly survey the vision and goals of on-the-fly (OTF) computing. Then we turn to heterogeneous multi-cores which, as platforms for OTF computing scenarios, have to support a high dynamics in both the workload and the system state. We argue that concepts and models of self-awareness studied in, for example, psychology, have been successfully transferred to the computing domain and help create systems that can autonomously adapt to changes in their state and environment in order to meet optimization goals and constraints.

关键词： software Engines hardware Actuators Computational modeling Adaptation models Multicore processing

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The control platform for decomposition and synthesis of specialized CNC systems 48

The control platform for decomposition and synthesis of spec...

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48th CIRP international conference on Manufacturing systems (CIRP CMS)

作者： Grigoriev, Sergej N. Martinov, Georgi M. Moscow State Technol Univ STANKIN Vadkovsky Per 3a Moscow 127055 Russia

Modem CNC systems applicability to prospective production technologies is investigated. A systematic approach to building the control platform and creating on its base specialized CNC systems is proposed. The application of the decomposition method in CNC systems allows allocating a limited, but extensible set of software and hardware components that implement the treatment technology, and construct a matrix of solutions for the subsequent synthesis of specialized CNC systems. synthesis is performed by arranging the hardware and software modules that create a control system according a particular processing facility. The creation of specialized CNC system for multi-tasking planning and milling machine is illustrated. (C) 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://***/licenses/by-nc-nd/4.0/).

关键词： control platform specialized CNC systems multi-tasking machining five-axis planning and milling machine

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Big data analytics on heterogeneous accelerator architectures

Big data analytics on heterogeneous accelerator architecture...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Katayoun Neshatpour Avesta Sasan Houman Homayoun Electrical and Computer Engineering Department George Mason University

ISBN: (纸本)9781509035908

In this paper, we present the implementation of big data analytics applications in a heterogeneous CPU+FPGA accelerator architecture. We develop the MapReduce implementation of K-means, K nearest neighbor, support vector machine and Naive Bayes in a Hadoop Streaming environment that allows developing mapper/reducer functions in a non-Java based language suited for interfacing with FPGA-based hardware accelerating environment. We present a full implementation of the HW+SW mappers on the Zynq FPGA platform. A promising speedup as well as energy-efficiency gains of upto 4.5X and 22X is achieved, respectively, in an end-to-end Hadoop implementation.

关键词： Acceleration Field programmable gate arrays hardware Big data Energy efficiency Accelerator architectures

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Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping

Fast and cycle-accurate simulation of multi-threaded applica...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ehsan Saboori Samar Abdi Concordia University Montreal Canada

ISBN: (纸本)9781509035908

This paper presents a fast and cycle accurate simulation environment for early power-performance analysis of multi-threaded applications targeted to symmetric multiprocessing embedded architectures. Our simulation environment leverages the hybrid prototyping technique, where a lightweight emulation kernel performs logical simulation of multiple identical cores on top of a single physical instance of a core. The technique does not require a detailed timing model of the core hardware because the application threads execute directly on the target core. Previous work on hybrid prototyping supported modeling of only statically scheduled threads, thereby severely limiting its modeling capabilities. In this work, we describe the modeling of dynamic RTOS scheduler as well as hardware interrupts on top of the emulation kernel, in order to support the simulation of unmodified multi-threaded applications. Our experimental results demonstrate the high accuracy, simulation speed and scalability of our hybrid prototyping-based simulation models.

关键词： hardware Multicore processing Kernel Prototypes Emulation Field programmable gate arrays

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Security and privacy challenges in IoT-based machine-to-machine collaborative scenarios

Security and privacy challenges in IoT-based machine-to-mach...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hsin Chung Chen Mohammad Abdullah Al Faruque Pai H. Chou Center for Embedded and Cyber-Physical Systems University of California Irvine CA USA

ISBN: (纸本)9781509035908

Currently, the IoT discussion is focused primarily on the operational phase. This includes how a IoT device behaves, operates, communicates, and interacts with other IoT devices during operation. However, IoT devices and systems have other lifecycle phases before and after operation. This extended abstract provides an overview of how other IoT lifecycle phases (e.g., design and service) can be improved with information feedback and feedforward flows between them. Digital Twins are a new mechanism to manage IoT devices and IoT systems-of-systems throughout their lifecycle. We present our vision on the industrial IoT lifecycle managed and optimized at scale via Digital Twins.

关键词： Security Privacy Collaboration Sensors Entropy Radio frequency hardware

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How to enable software isolation and boost system performance with sub-block erase over 3D flash memory

How to enable software isolation and boost system performanc...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hsin-Yu Chang Chien-Chung Ho Yuan-Hao Chang Yu-Ming Chang Tei-Wei Kuo Department of Computer Science and Information Engineering National Taiwan University Institute of Information Science Academia Sinica Macronix International Co. Ltd. Taiwan Research Center for Information Technology Innovation Academia Sinica

ISBN: (纸本)9781509035908

The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability problem, that is already severe to 3D flash memory. In this work, we propose a sub-block erase design to not only alleviate the write amplification problem by reducing live-page copying but also improve the system reliability with a software isolation strategy. In particular, sub-blocks are carefully allocated to satisfy write requests so as to reduce disturbance by using free or invalid sub-blocks as isolation layers among sub-blocks, without additional hardware cost and capacity loss. A series of experiments were conducted to evaluate the capability of the proposed design. The results show that the proposed design is very effective in improving the system performance by reducing garbage collection overheads and in improving the device reliability/lifetime.

关键词： hardware Three-dimensional displays software Market research system performance Reliability engineering

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