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Computer Security by hardware-Intrinsic Authentication

Computer Security by Hardware-Intrinsic Authentication

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Hoffman, Caio Cortes, Mario Aranha, Diego F. Araujo, Guido Univ Estadual Campinas Inst Comp Campinas SP Brazil

ISBN: (纸本)9781467383219

The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things ( IoT), has raised a number of challenges for the design of systems-on-Chip ( SoCs) devices. Tiny manufacturing costs, stringent security, and ultra-low power operation constraints have considerably raised SoC design requirements. More than incremental approaches which try to re-use current cryptographic mechanisms, the new generation of IoT devices will require novel solutions which deeply integrate their hardware-intrinsic features to program execution. This paper proposes a low-cost PUF-based authentication architecture aiming to secure code execution in IoT SoCs. The solution is deeply embedded into the processor micro-architecture, so as to minimize re-design costs and performance penalties. This new architecture model not only deals with the most common threats against code and data authenticity and integrity, but also provides an approach to extract from processor's caches a stable and unpredictable key that is used in the code and data authentication process.

关键词： Internet of Things authorisation cache storage computer architecture cryptography data integrity system-on-chip Internet of the things IoT SoC computer security cryptographic mechanisms daily-life objects data authentication process data authenticity electronic devices hardware-intrinsic authentication hardware-intrinsic features low-cost PUF-based authentication architecture processor caches processor microarchitecture systems-on-chip device design Authentication Computer architecture Cryptography Performance evaluation Random access memory software Computer Architecture Data Quality cryptography Computer Security system-on-chip Electron devices random access machine cache storage Internet of things Authentication Authorization Performance Evaluation computer software

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Design methodologies for securing cyber-physical systems

Design methodologies for securing cyber-physical systems

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international conference on hardware/software codesign and system synthesis, CODES+ISSS 2015

作者： Faruque, Mohammad Al Regazzoni, Francesco Pajic, Miroslav Dept. of Electrical Engineering and Computer Science University of California IrvineCA United States ALaRI Institute University of Lugano Lugano Switzerland Dept. of Electrical and Computer Engineering Duke University Durham NC United States

ISBN: (纸本)9781467383219

Cyber-Physical systems (CPS) are in most cases safety- and mission-critical. Standard design techniques used for securing embedded systems are not suitable for CPS due to the restricted computation and communication budget available in the latter. In addition, the sensitivity of sensed data and the presence of actuation components further increase the security requirements of CPS. To address these issues, it is necessary to provide new design methods in which security is considered from the beginning of the whole design flow and addressed in a holistic way. In this paper, we focus on the design of secure CPS as part of the complete CPS design process, and provide insights into new requirements on platform-aware design of control components, design methodologies and architectures posed by CPS design. We start by discussing methods for the multi-disciplinary modeling, simulation, tools, and software synthesis challenges for CPS. We also present a framework for design of secure control systems for CPS, while taking into account properties of the underlying computation and communication platforms. Finally, we describe the security challenges in the computing hardware that is used in CPS. © 2015 IEEE.

关键词： Cyber Physical system

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Completeness Bounds and Sequentialization for Model Checking of Interacting Firmware and hardware

Completeness Bounds and Sequentialization for Model Checking...

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Ahn, Sunha Malik, Sharad Gupta, Aarti Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)9781467383219

An emerging trend in system design is to implement complex system management functions in firmware ( FW). This changing design scenario requires support for verifying FW in the context of its hardware ( HW) environment. As shown in previous work, there is value in a unified HW-FW model for driving the verification tasks. This model can help identify specific commonly-occurring interaction patterns between the HW and FW. These patterns enable pruning the verification search space as demonstrated in previous work in automating FW test generation using concolic testing. In this work, we introduce a bounded model checking ( BMC)-based methodology for FW verification. Although BMC is effective for finding bugs by unrolling the underlying transition system up to some bound, it requires a completeness threshold on the bound to ensure complete verification. We show how commonly occurring FW code patterns can be exploited, using inexpensive static analysis techniques, to determine this completeness bound. Further, we show how this bound analysis, combined with the interaction patterns in the unified HW-FW model, is used to sequentialize the concurrent FW and HW code, i. e., to derive a sequential program that represents the parallel interaction of the FW and HW. This enables the direct application of standard software model checkers such as CBMC on this sequentialized program. We have automated this process by implementing: ( i) a static completeness bound analyzer on top of the tool Frama-C, and ( ii) a sequentializer to generate code for verification by the CBMC model checker. We evaluate the resulting tool using three real FW benchmarks, each consisting of a Linux device driver and its interacting QEMU-emulated HW code with multiple correctness properties. We successfully computed the BMC completeness bounds for 41 out of 46 properties and completed model checking for 12 out of 16 FW transactions.

关键词： Firmware

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Power-awareness and smart-resource management in embedded computing systems

Power-awareness and smart-resource management in embedded co...

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Santambrogio, M. D. Ayala, Jose L. Campanoni, Simone Cattaneo, R. Durelli, G. C. Ferroni, M. Nacci, A. Pagan, J. Zapater, M. Vallejo, M. Politecn Milan DEIB I-20133 Milan Italy Univ Complutense Madrid DACYA E-28040 Madrid Spain Northwestern Univ EELS Evanston IL USA UPM CCS Madrid Spain Univ Nacl Colombia Dept Elect Energy Automat Grp UNAL Bogota Colombia Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy Univ Complutense Madrid DACYA Ctr Computat Simulat E-28040 Madrid Spain Univ Nacl Colombia Dept Elect Energy Automat Grp UNAL Bogota Colombia

ISBN: (纸本)9781467383219

Resources such as quantities of transistors and memory, the level of integration and the speed of components have increased dramatically over the years. Even though the technologies have improved, we continue to apply outdated approaches to our use of these resources. Key computer science abstractions have not changed since the 1960's. Therefore this is the time for a fresh approach to the way systems are designed and used.

关键词： embedded systems power aware computing computer science abstraction embedded computing system power-awareness smart-resource management Accuracy Distortion Multicore processing Parallel processing Program processors Runtime Semantics power aware computing Program processors Embedded computing Runtime PARALLEL PROCESSING (COMPUTERS) Embedded systems Semantics abnormal shapes distortion semiotics

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Run-DMC: Runtime Dynamic Heterogeneous Multicore Performance and Power Estimation for Energy Efficiency

Run-DMC: Runtime Dynamic Heterogeneous Multicore Performance...

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Muck, Tiago Sarma, Santanu Dutt, Nikil Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA

ISBN: (纸本)9781467383219

In this paper we propose Run-DMC, an accurate runtime performance and power estimation scheme for dynamic workloads executing on heterogeneous multicore systems. In contrast to previous works, Run-DMC uses fine grain per-thread metrics that model the Thread Load Contribution ( TLC) induced by the native OS scheduling policy to accurately predict performance and power for any possible thread-to-core mapping. This allows the operating system to opportunistically exploit the heterogeneous multicore architecture by dynamically mapping workloads to the most appropriate core type. We have integrated our models into the Linux kernel running on top of a heterogeneous multicore system with 4 different core types. Our experimental results show that Run-DMC models yield up to 97% more energy efficient when compared to the vanilla Linux. When compared to the approach employed by state-of-the-art energy-aware schedulers, Run-DMC yields up-to 44% better energy efficiency.

关键词： Linux energy conservation multi-threading multiprocessing systems power aware computing processor scheduling Linux kernel OS scheduling policy TLC dynamic mapping workloads energy efficiency fine grain per-thread metrics heterogeneous multicore architecture heterogeneous multicore systems operating system power estimation run-DMC runtime dynamic heterogeneous multicore performance thread load contribution thread-to-core mapping vanilla Linux Estimation Instruction sets Load modeling Measurement Multicore processing Runtime Sensors power estimation Energy efficiency power aware computing instruction sets Runtime Operating systems Linux Multiprocessing systems Multithreading scheduling of multiprocessor Load modeling Energy conservation Multi-core processors Sensors core type

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Development and application of remote laboratory for embedded systems design 12

Development and application of remote laboratory for embedde...

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2015 12th international conference on Remote Engineering and Virtual Instrumentation, REV 2015

作者： Parkhomenko, Anzhelika Gladkova, Olga Ivanov, Eugene Sokolyanskii, Aleksandr Kurson, Sergey Zaporizhzhya National Technical University Software Tools Department Zaporizhzhya Ukraine

ISBN: (纸本)9781479978397

This paper devoted to Embedded systems' hardware-software codesign and an overview of approach based on using ready platforms. Comparable analysis of well-known platforms from different vendors is given. Application of remote laboratories of the embedded system rapid prototyping was offered. Remote lab architecture, set of experiments and use case scenario are described. Proposed approach improves the current state of the art in the area of embedded systems design allowing to accelerate stages of hardware-software integration and testing. © 2015 IEEE.

关键词： Embedded systems

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Big/Little Deep Neural Network for Ultra Low Power Inference

Big/Little Deep Neural Network for Ultra Low Power Inference

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IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Park, Eunhyeok Kim, Dongyoung Kim, Soobeom Kim, Yong-Deok Kim, Gunhee Yoon, Sungroh Yoo, Sungjoo Seoul Natl Univ Comp Memory Architecture Lab Seoul 151 South Korea Samsung Elect Device Solut Software R&D Ctr Suwon South Korea Seoul Natl Univ Vis & Learning Lab Seoul 151 South Korea Seoul Natl Univ Adv Comp Lab Seoul 151 South Korea

ISBN: (纸本)9781467383219

Deep neural networks ( DNNs) have recently proved their effectiveness in complex data analyses such as object/speech recognition. As their applications are being expanded to mobile devices, their energy efficiencies are becoming critical. In this paper, we propose a novel concept called big/LITTLE DNN ( BL-DNN) which significantly reduces energy consumption required for DNN execution at a negligible loss of inference accuracy. The BL-DNN consists of a little DNN ( consuming low energy) and a full-fledged big DNN. In order to reduce energy consumption, the BL-DNN aims at avoiding the execution of the big DNN whenever possible. The key idea for this goal is to execute the little DNN first for inference ( without big DNN execution) and simply use its result as the final inference result as long as the result is estimated to be accurate. On the other hand, if the result from the little DNN is not considered to be accurate, the big DNN is executed to give the final inference result. This approach reduces the total energy consumption by obtaining the inference result only with the little, energy-efficient DNN in most cases, while maintaining the similar level of inference accuracy through selectively utilizing the big DNN execution. We present design-time and runtime methods to control the execution of big DNN under a trade-off between energy consumption and inference accuracy. Experiments with state-of-the-art DNNs for ImageNet and MNIST show that our proposed BL-DNN can offer up to 53.7% ( ImageNet) and 94.1% ( MNIST) reductions in energy consumption at a loss of 0.90% ( ImageNet) and 0.12% ( MNIST) in inference accuracy, respectively.

关键词： Deep neural network low power

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COMET: Communication-optimised multi-threaded error-detection technique

COMET: Communication-optimised multi-threaded error-detectio...

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proceedings of the international conference on Compilers, Architectures and synthesis for Embedded systems (CASES)

作者： Konstantina Mitropoulou Vasileios Porpodas Timothy M. Jones Computer Laboratory University of Cambridge UK Intel USA

ISBN: (纸本)9781509035892

Relentless technology scaling has made transistors more vulnerable to soft, or transient, errors. To keep systems robust against these, current error detection techniques use different types of redundancy at the hardware or the software level. A consequence of these additional protection mechanisms is that these systems tend to become slower. In particular, software error-detection techniques degrade performance considerably, limiting their uptake. This paper focuses on software redundant multi-threading error detection, a compiler-based technique that makes use of redundant cores within a multi-core system to perform error checking. Implementations of this scheme feature two threads that execute almost the same code: the main thread runs the original code and the checker thread executes code to verify the correctness of the original. The main thread communicates the values that require checking to the checker thread to use in its comparisons. We identify a major performance bottleneck in existing schemes: poorly performing inter-core communication and the generated code associated with it. Our study shows this is a major performance impediment within existing techniques since the two threads require extremely fine-grained communication, on the order of every few instructions. We alleviate this bottleneck with a series of code generation optimisations at the compiler level. We propose COMET (Communication-Optimised Multi-threaded Error-detection Technique), which improves performance across the NAS parallel benchmarks by 31.4% (on average) compared to the state-of-the-art, without affecting fault-coverage.

关键词： Instruction sets Optimization Synchronization Transient analysis hardware Transistors

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Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip

Handling large data sets for high-performance embedded appli...

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proceedings of the international conference on Compilers, Architectures and synthesis for Embedded systems (CASES)

作者： Paolo Mantovani Emilio G. Cota Christian Pilato Giuseppe Di Guglielmo Luca P. Carloni Department of Computer Science Columbia University New York NY USA

ISBN: (纸本)9781509035892

Local memory is a key factor for the performance of accelerators in SoCs. Despite technology scaling, the gap between on-chip storage and memory footprint of embedded applications keeps widening. We present a solution to preserve the speedup of accelerators when scaling from small to large data sets. Combining specialized DMA and address translation with a software layer in Linux, our design is transparent to user applications and broadly applicable to any class of SoCs hosting high-throughput accelerators. We demonstrate the robustness of our design across many heterogeneous workload scenarios and memory allocation policies with FPGA-based SoC prototypes featuring twelve concurrent accelerators accessing up to 768MB out of 1GB-addressable DRAM.

关键词： Program processors Random access memory system-on-chip hardware Linux Computer architecture

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Loop Coarsening in C-based High-Level synthesis 26

Loop Coarsening in C-based High-Level Synthesis

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26th international conference on Application-Specific systems, Architectures and Processors (ASAP)

作者： Schmid, Moritz Reiche, Oliver Hannig, Frank Teich, Juergen Univ Erlangen Nurnberg Dept Comp Sci Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9781479919253

Current tools for High-Level synthesis (HLS) excel at exploiting Instruction-Level Parallelism (ILP), the support for Data-Level Parallelism (DLP), one of the key advantages of Field Programmable Gate Arrays (FPGAs), is in contrast very limited. This work examines the exploitation of DLP on FPGAs using code generation for C-based HLS of image filters and streaming pipelines, consisting of point and local operators. In addition to well known loop tiling techniques, we propose loop coarsening, which delivers superior performance and scalability. Loop tiling corresponds to splitting an image into separate regions, which are then processed in parallel by replicated accelerators. For data streaming, this also requires the generation of glue logic for the distribution of image data. Conversely, loop coarsening allows to process multiple pixels in parallel, whereby only the kernel operator is replicated within a single accelerator. We augment the FPGA back end of the heterogeneous DomainSpecific Language (DSL) framework HIPAcc by loop coarsening and compare the resulting FPGA accelerators to highly optimized software implementations for Graphics Processing Units (GPUs), all generated from the exact same code base. Moreover, we demonstrate the advantages of code generation for algorithm development by outlining how design space exploration enabled by HIPAcc can yield a more efficient implementation than handcoded VHDL.

关键词： Field programmable gate arrays Code generation Coarsening Loops Contraceptive Coil TXNL4B gene digital light processor(DLP) image filtering high level synthesis code base local operator Parallel Lines image data Space Exploration hue lightness saturation

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