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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1556 条记录，以下是331-340 订阅

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Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip

Handling large data sets for high-performance embedded appli...

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proceedings of the international conference on Compilers, Architectures and synthesis for Embedded systems (CASES)

作者： Paolo Mantovani Emilio G. Cota Christian Pilato Giuseppe Di Guglielmo Luca P. Carloni Department of Computer Science Columbia University New York NY USA

ISBN: (纸本)9781509035892

Local memory is a key factor for the performance of accelerators in SoCs. Despite technology scaling, the gap between on-chip storage and memory footprint of embedded applications keeps widening. We present a solution to preserve the speedup of accelerators when scaling from small to large data sets. Combining specialized DMA and address translation with a software layer in Linux, our design is transparent to user applications and broadly applicable to any class of SoCs hosting high-throughput accelerators. We demonstrate the robustness of our design across many heterogeneous workload scenarios and memory allocation policies with FPGA-based SoC prototypes featuring twelve concurrent accelerators accessing up to 768MB out of 1GB-addressable DRAM.

关键词： Program processors Random access memory system-on-chip hardware Linux Computer architecture

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Loop Coarsening in C-based High-Level synthesis 26

Loop Coarsening in C-based High-Level Synthesis

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26th international conference on Application-Specific systems, Architectures and Processors (ASAP)

作者： Schmid, Moritz Reiche, Oliver Hannig, Frank Teich, Juergen Univ Erlangen Nurnberg Dept Comp Sci Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9781479919253

Current tools for High-Level synthesis (HLS) excel at exploiting Instruction-Level Parallelism (ILP), the support for Data-Level Parallelism (DLP), one of the key advantages of Field Programmable Gate Arrays (FPGAs), is in contrast very limited. This work examines the exploitation of DLP on FPGAs using code generation for C-based HLS of image filters and streaming pipelines, consisting of point and local operators. In addition to well known loop tiling techniques, we propose loop coarsening, which delivers superior performance and scalability. Loop tiling corresponds to splitting an image into separate regions, which are then processed in parallel by replicated accelerators. For data streaming, this also requires the generation of glue logic for the distribution of image data. Conversely, loop coarsening allows to process multiple pixels in parallel, whereby only the kernel operator is replicated within a single accelerator. We augment the FPGA back end of the heterogeneous DomainSpecific Language (DSL) framework HIPAcc by loop coarsening and compare the resulting FPGA accelerators to highly optimized software implementations for Graphics Processing Units (GPUs), all generated from the exact same code base. Moreover, we demonstrate the advantages of code generation for algorithm development by outlining how design space exploration enabled by HIPAcc can yield a more efficient implementation than handcoded VHDL.

关键词： Field programmable gate arrays Code generation Coarsening Loops Contraceptive Coil TXNL4B gene digital light processor(DLP) image filtering high level synthesis code base local operator Parallel Lines image data Space Exploration hue lightness saturation

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hardware synthesis from a recursive functional language 15

Hardware synthesis from a recursive functional language

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Kuangya Zhai Richard Townsend Lianne Lairmore Martha A. Kim Stephen A. Edwards Columbia University

ISBN: (纸本)9781467383219

Abstraction in hardware description languages stalled at the register-transfer level decades ago, yet few alternatives have had much success, in part because they provide only modest gains in expressivity. We propose to make a much larger jump: a compiler that synthesizes hardware from behavioral functional specifications. Our compiler translates general Haskell programs into a restricted intermediate representation before applying a series of semantics-preserving transformations, concluding with a simple syntax-directed translation to systemVerilog. Here, we present the overall framework for this compiler, focusing on the intermediate representations involved and our method for translating general recursive functions into equivalent hardware. We conclude with experimental results that depict the performance and resource usage of the circuitry generated with our compiler.

关键词： hardware Program processors Transforms Algorithm design and analysis IP networks Pattern matching

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GP-based Methodology for HW/SW Co-synthesis of Multiprocessor Embedded systems with Increasing Number of Individuals Obtained by Mutation 5

GP-based Methodology for HW/SW Co-synthesis of Multiprocesso...

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5th international conference on Pervasive and Embedded Computing and Communication systems (PECCS)

作者： Gorski, Adam Ogorzalek, Maciej Jagiellonian Univ Cracow Dept Informat Technol Reymonta 4 Krakow Poland

ISBN: (纸本)9789897581373

In this work, a genetic programming methodology for co-synthesis of multiprocessor systems is presented. Genotype is a tree which nodes include system construction procedures. Thus the design methodology is evolving. Next generations are obtained using genetic operators: mutation, reproduction and crossover. Unlike other algorithms in presented methodology number of individuals obtained by mutation operator is not const. Therefore number of individuals in each population is increasing. The size of final generation is found by the algorithm.

关键词： Embedded systems Genetic Programming Genetic Algorithm Architecture hardware/software Co-Design Multiprocessor system

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Redesigning a tagless access buffer to require minimal ISA changes

Redesigning a tagless access buffer to require minimal ISA c...

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proceedings of the international conference on Compilers, Architectures and synthesis for Embedded systems (CASES)

作者： Carlos Sanchez Peter Gavin Daniel Moreau Magnus Själander David Whalley Per Larsson-Edefors Sally A. McKee Florida State University USA Chalmers University of Technology Sweden NTNU Norway Uppsala University Sweden

Energy efficiency is a first-order design goal for nearly all classes of processors, but it is particularly important in mobile and embedded systems. Data caches in such systems account for a large portion of the processor's energy usage, and thus techniques to improve the energy efficiency of the cache hierarchy are likely to have high impact. Our prior work reduced data cache energy via a tagless access buffer (TAB) that sits at the top of the cache hierarchy. Strided memory references are redirected from the level-one data cache (L1D) to the smaller, more energy-efficient TAB. These references need not access the data translation lookaside buffer (DTLB), and they can avoid unnecessary transfers from lower levels of the memory hierarchy. The original TAB implementation requires changing the immediate field of load and store instructions, necessitating substantial ISA modifications. Here we present a new TAB design that requires minimal instruction set changes, gives software more explicit control over TAB resource management, and remains compatible with legacy (non-TAB) code. With a line size of 32 bytes, a four-line TAB can eliminate 31% of L1D accesses, on average. Together, the new TAB, L1D, and DTLB use 22% less energy than a TAB-less hierarchy, and the TAB system decreases execution time by 1.7%.

关键词： Prefetching Registers Metadata hardware Indexes Organizations

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The shift to multicores in real-time and safety-critical systems 15

The shift to multicores in real-time and safety-critical sys...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Selma Saidi Rolf Ernst Sascha Uhrig Henrik Theiling Benoît Dupont de Dinechin Technische Universität Braunschweig Airbus Group Innovations SYSGO AG Mainz Germany Kalray SA

ISBN: (纸本)9781467383219

In real-time and safety-critical systems, the move towards multicores is becoming unavoidable in order to keep pace with the increasing required processing power and to meet the high integration trend while maintaining a reasonable power consumption. However, standard multicore systems are mainly designed to increase average performance, whereas embedded systems have additional requirements with respect to safety, reliability and realtime behavior. Therefore, the shift to multicores raises several challenges the embedded community has to face. These challenges involve the design of certifiable multicore platforms, the management of shared resources and the development/integration of parallel software. These issues are encountered at different steps of system development, from modeling and design to software implementation and hardware deployment. Therefore, both multi-core/semiconductor manufacturers and the real-time community have to bridge the gap in order to meet the challenges imposed by multicores. The goal of this paper is to trigger such a discussion as an attempt to bridge the gap between the two worlds and to raise awareness about the hurdles and challenges that need to be tackled.

关键词： Multicore processing software Aerospace electronics Safety hardware Timing Real-time systems

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Computer security by hardware-intrinsic authentication 15

Computer security by hardware-intrinsic authentication

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Caio Hoffman Mario Cortes Diego F. Aranha Guido Araujo Institute of Computing University of Campinas

ISBN: (纸本)9781467383219

The widespread embedding of electronic devices into the daily-life objects, and their integration in the so called Internet of the Things (IoT), has raised a number of challenges for the design of systems-on-Chip (SoCs) devices. Tiny manufacturing costs, stringent security, and ultra-low power operation constraints have considerably raised SoC design requirements. More than incremental approaches which try to re-use current cryptographic mechanisms, the new generation of IoT devices will require novel solutions which deeply integrate their hardware-intrinsic features to program execution. This paper proposes a low-cost PUF-based authentication architecture aiming to secure code execution in IoT SoCs. The solution is deeply embedded into the processor micro-architecture, so as to minimize re-design costs and performance penalties. This new architecture model not only deals with the most common threats against code and data authenticity and integrity, but also provides an approach to extract from processor's caches a stable and unpredictable key that is used in the code and data authentication process.

关键词： Computer architecture Authentication Cryptography Performance evaluation software Random access memory

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Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs 15

Lightweight virtual memory support for many-core accelerator...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Pirmin Vogel Andrea Marongiu Luca Benini Integrated Systems Laboratory ETH Zurich Switzerland Electrical Electronic and Information Engineering University of Bologna Italy

ISBN: (纸本)9781467383219

While high-end heterogeneous systems are increasingly supporting heterogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous system Architecture (HSA) foundation, their low-power counterparts targeting the embedded domain still lack basic features like virtual memory support for accelerators. As opposed to simply passing virtual address pointers, explicit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance. In this work, we present a mixed hardware/software solution to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded systems-on-chip (SoCs). Based on an input/output translation lookaside buffer (IOTLB), efficiently managed by a kernel-level driver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units. Using our evaluation platform based on the Xilinx Zynq-7000 SoC with a many-core accelerator implemented in the programmable logic, we demonstrate the effectiveness of our solution and the benefits of virtual memory support for embedded heterogeneous SoCs.

关键词： Kernel Memory management Programming hardware Random access memory Complexity theory Prefetching

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Transparent and portable agent based task migration for data-flow applications on multi-tiled architectures 15

Transparent and portable agent based task migration for data...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ashaf El-Antably Olivier Gruber Frederic Rousseau Nicolas Fournel TIMA lab - CNRS/UJF/Grenoble INP Grenoble France LIG - CNRS/UJF/Grenoble INP Grenoble France

ISBN: (纸本)9781467383219

Fully distributed memory multi-processors (MPSoC) implemented in multi-tiled architectures are promising solutions to support modern sophisticated applications, however, reliability of such systems is always an issue. As a result, system-level solution like task migration keeps its importance. Transferring the execution of a task from one tile to another helps keep acceptable reliability of such systems. A tile contains at least one processor and associated peripherals with a communication device responsible for inter-tile communications. We propose in this work a task migration technique that targets data-flow applications running on multi-tiled architectures. This technique uses a middleware layer that makes it transparent to application programmers and eases its portability over different multi-tiled architectures. It can be deployed on small operating systems that support neither MMU nor dynamic loading for task code. We show that this technique is operational on x86 based real hardware platform. Experimental results show low overhead both in memory and performance without much variance.

关键词： Context Operating systems Memory architecture hardware Loading Runtime

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Optimized Indoor Positioning Based on WIFI in Mobile Classroom Project 11

Optimized Indoor Positioning Based on WIFI in Mobile Classro...

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11th international conference on Natural Computation (ICNC) / 12th international conference on Fuzzy systems and Knowledge Discovery (FSKD)

作者： Guo, Jianhui Liu, Xianzhong Wang, Zhongzhu East China Normal Univ Inst Software Engn Shanghai Peoples R China East China Normal Univ Inst Software Engn Software Hardware Codesign Engn Res Ctr MoE Shanghai Peoples R China

ISBN: (纸本)9781467376792

The Mobile Classroom Project aims at building an interactive platform between students and teachers. The LBS(Location Based Services) Teaching Platform is an important part of it. With its help, teachers can send homework, in-class exercises or related learning materials to students, which take mobile teaching equipment in the classroom. Students can submit their homework and in-class test in specified location quickly. The indoor positioning system is the foundation of the LBS teaching platform. However, the current indoor localization based on WIFI(Wireless Fidelity) fingerprint cannot consider both effects of environment to AP(Access Point) and complexity of localization algorithm, leading to the result of low location accuracy or consume more resources of mobile equipment. This paper proposes an optimized Indoor Positioning algorithm based on WIFI. It uses a reliable AP algorithm as AP selection algorithm to reduce the effects of the indoor environment, and takes reliable AP algorithm combining hybrid of KNN(K-Nearest Neighbor) and Bayesian decision into account to obtain better location accuracy and to reduce complexity of positioning computation possibly. In this paper, we realized the indoor positioning system and gave the experiments. We can see the location accuracy is improved and the complexity of the algorithm is reduced.

关键词： Mobile Classroom Indoor positioning WIFI fingerprint reliable AP

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