检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,499 篇 会议
55 篇 期刊文献

馆藏范围

1,554 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

799 篇 工学
- 738 篇 计算机科学与技术...
- 560 篇 软件工程
- 153 篇 电气工程
- 135 篇 电子科学与技术（可...
- 103 篇 信息与通信工程
- 74 篇 控制科学与工程
- 22 篇 机械工程
- 13 篇 动力工程及工程热...
- 11 篇 光学工程
- 10 篇 建筑学
- 9 篇 仪器科学与技术
- 9 篇 生物工程
- 8 篇 材料科学与工程（可...
- 8 篇 土木工程
- 8 篇 生物医学工程（可授...
- 7 篇 安全科学与工程
- 6 篇 航空宇航科学与技...
179 篇 理学
- 104 篇 数学
- 48 篇 系统科学
- 39 篇 物理学
- 16 篇 统计学（可授理学、...
- 9 篇 生物学
- 6 篇 化学
108 篇 管理学
- 89 篇 管理科学与工程(可...
- 29 篇 工商管理
- 23 篇 图书情报与档案管...
15 篇 法学
- 11 篇 社会学
5 篇 经济学
- 5 篇 应用经济学
5 篇 教育学
- 5 篇 教育学
5 篇 医学
- 5 篇 临床医学
4 篇 艺术学
1 篇 农学

主题

359 篇 hardware
177 篇 computer archite...
162 篇 embedded system
135 篇 application soft...
87 篇 field programmab...
83 篇 embedded systems
75 篇 control system s...
69 篇 costs
67 篇 high level synth...
65 篇 computational mo...
65 篇 algorithm design...
64 篇 system-on-a-chip
63 篇 permission
63 篇 embedded softwar...
61 篇 real time system...
52 篇 timing
50 篇 system-on-chip
48 篇 computer science
47 篇 energy consumpti...
46 篇 space exploratio...

机构

10 篇 department of el...
8 篇 univ calif river...
8 篇 center for embed...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 department of co...
5 篇 princeton univ d...
5 篇 school of inform...
5 篇 department of co...
5 篇 philips research...
5 篇 institute for in...
5 篇 technische unive...
4 篇 department of el...
4 篇 ibm thomas j. wa...
4 篇 imec leuven
4 篇 politecn torino ...
4 篇 university of er...
4 篇 tu braunschweig
4 篇 university of do...

作者

9 篇 sri parameswaran
9 篇 ogras umit y.
9 篇 parameswaran sri
9 篇 nikil dutt
7 篇 rolf ernst
7 篇 dick robert p.
7 篇 dutt nikil
7 篇 robert p. dick
7 篇 leupers rainer
7 篇 vahid f
6 篇 jiang wei
6 篇 greg stitt
6 篇 teich juergen
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
6 篇 a. sangiovanni-v...
6 篇 r. ernst
6 篇 jha niraj k.
5 篇 sungjoo yoo

语言

1,535 篇 英文
17 篇 其他
2 篇 中文

检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1554 条记录，以下是341-350 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

hardware implementation of Offset Codebook Mode 3 authenticated encryption 30

Hardware implementation of Offset Codebook Mode 3 authentica...

引用

30th international conference on Computers and Their Applications, CATA 2015

作者： Clift, Pamela Arad, Behnam S. Department of Computer Science California State University Sacramento SacramentoCA95819 United States

ISBN: (纸本)9781880843987

Encryption ensures protection of important information, corporate secrets, classified information, and private information. Along with protecting data, we need to ensure that the data is coming from an authorized source. Authentication and encryption combined ensure the integrity of the data. Authenticated-encryption has become popular to minimize impact of attacks by hackers. Offset Codebook Mode3 (OCB3) is a new authenticated encryption mode algorithm developed by Krovetz and Rogaway. OCB3 is built from a block cipher using a counter mode with a nonce. Krovetz and Rogaway compared the algorithm to other authenticated encryption algorithms such as GCM1 and CCM2. They made enhancements to OCB in order to improve its performance beyond that of GCM. hardware implementation of an encryption algorithm is an important alternative to software implementation as it can operate more efficiently. We proposed a hardware model of the OCB3 algorithm in system Verilog hardware description language. The proposed hardware model of OCB3 was validated thoroughly using an elaborate test bench that utilized advanced system Verilog verification features. The validated design was synthesized to an optimized gate-level representation using a 90 nm technology library. synthesis results showed that the design could easily run at 166MHz. Copyright © 2015 by The international Society for Computers and Their Applications (ISCA).

关键词： Cryptography

来源：评论

学校读者我要写书评

暂无评论

dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations 15

dsReliM: Power-constrained reliability management in Dark-Si...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Mohammad Salehi Muhammad Shafique Florian Kriebel Semeen Rehman Mohammad Khavari Tavana Alireza Ejlali Jörg Henkel Karlsruhe Institute of Technology (KIT) Germany Department of Computer Engineering Sharif University of Technology Tehran Iran Department of Electrical and Computer Engineering George Mason University Fairfax Virginia USA

ISBN: (纸本)9781467383219

Due to the tight power envelope, in the future technology nodes it is envisaged that not all cores in a many-core chip can be simultaneously powered-on (at full performance level). The power-gated cores are referred to as Dark Silicon. At the same time, growing reliability issues due to process variations and soft errors challenge the cost-effective deployment of future technology nodes. This paper presents a reliability management system for Dark Silicon chips (dsReliM) that optimizes for reliability of on-chip systems while jointly accounting for soft errors, process variations and the thermal design power (TDP) constraint. Towards the TDP-constrained reliability optimization, dsReliM leverages multiple reliable application versions that can potentially execute on different cores with frequency variations and supporting differenst voltage-frequency levels, thus facilitating distinct power, reliability and performance tradeoffs at run time. Experiments show that our dsReliM system provides up to 20% reliability improvements under different TDP constraints when compared to a state-of-the-art technique. Also, compared to an ideal-case optimal solution, dsReliM deviates up to 2.5% in terms of reliability efficiency, but speeds up the reliability management decision time by a factor of up to 3100.

关键词： software reliability software Silicon Timing Management Transient analysis

来源：评论

学校读者我要写书评

暂无评论

Completeness bounds and sequentialization for model checking of interacting firmware and hardware 15

Completeness bounds and sequentialization for model checking...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Sunha Ahn Sharad Malik Aarti Gupta Princeton University

ISBN: (纸本)9781467383219

An emerging trend in system design is to implement complex system management functions in firmware (FW). This changing design scenario requires support for verifying FW in the context of its hardware (HW) environment. As shown in previous work, there is value in a unified HW-FW model for driving the verification tasks. This model can help identify specific commonly-occurring interaction patterns between the HW and FW. These patterns enable pruning the verification search space as demonstrated in previous work in automating FW test generation using concolic testing. In this work, we introduce a bounded model checking (BMC)-based methodology for FW verification. Although BMC is effective for finding bugs by unrolling the underlying transition system up to some bound, it requires a completeness threshold on the bound to ensure complete verification. We show how commonly occurring FW code patterns can be exploited, using inexpensive static analysis techniques, to determine this completeness bound. Further, we show how this bound analysis, combined with the interaction patterns in the unified HW-FW model, is used to sequentialize the concurrent FW and HW code, i.e., to derive a sequential program that represents the parallel interaction of the FW and HW. This enables the direct application of standard software model checkers such as CBMC on this sequentialized program. We have automated this process by implementing: (i) a static completeness bound analyzer on top of the tool Frama-C, and (ii) a sequentializer to generate code for verification by the CBMC model checker. We evaluate the resulting tool using three real FW benchmarks, each consisting of a Linux device driver and its interacting QEMU-emulated HW code with multiple correctness properties. We successfully computed the BMC completeness bounds for 41 out of 46 properties and completed model checking for 12 out of 16 FW transactions.

关键词： Model checking Context Benchmark testing hardware Analytical models Linux Registers

来源：评论

学校读者我要写书评

暂无评论

proceedings of the 12th ACM international conference on Computing Frontiers, CF 2015

Proceedings of the 12th ACM International Conference on Comp...

引用

12th ACM international conference on Computing Frontiers, CF 2015

ISBN: (纸本)9781450333580

The proceedings contain 65 papers. The topics discussed include: an empirical high level performance model for future many-cores;just-in-time component-wise power and thermal modeling;an instrumentation approach for hardware-agnostic software characterization;near threshold cloud processors for dark silicon mitigation: the impact on emerging scale-out workloads;data access optimization in a processing-in-memory system;genesis: a language for generating synthetic training programs for machine learning;a significance-driven programming framework for energy-constrained approximate computing;an evaluation and analysis of graph processing frameworks on five key issues;optimizing irregular applications for energy and performance on the tilera many-core architecture;hierarchical synthesis of quantum and reversible architectures;and cooperative repair based on tree structure for multiple failures in distributed storage systems with regenerating codes.

关键词：

来源：评论

学校读者我要写书评

暂无评论

proceedings of the international conference on Computer Sciences and Information Technologies, CSIT 2015

Proceedings of the International Conference on Computer Scie...

引用

10th international conference on Computer Sciences and Information Technologies, CSIT 2015

The proceedings contain 52 papers. The topics discussed include: synthesis of hardware components for vertical-group parallel neural networks;method of developing the behavior models in form of states diagram for complex information systems;distance measurement using radio frequency identification technology;intelligent advisory systems and information technology support for decision making in tourism;morphological processing of videostream frames binary masks;learning-based image super-resolution using weight coefficients of synaptic connections;algorithms for software clustering and modularization;statistics of parts of speech frequencies in Marko Cheremshyna’s works;retrieval and processing of information with the use of multi-agent system;cryptographic information protection using extended finite fields;and mathematical modeling of visco-elastic-plastic deformation in capillary-porous materials in the drying process.

关键词：

来源：评论

学校读者我要写书评

暂无评论

proceedings of the international conference on Computer Sciences and Information Technologies, CSIT 2015

Proceedings of the International Conference on Computer Scie...

引用

10th international conference on Computer Sciences and Information Technologies, CSIT 2015

ISBN: (纸本)9786176078159

The proceedings contain 51 papers. The topics discussed include: synthesis of hardware components for vertical-group parallel neural networks;method of developing the behavior models in form of states diagram for complex information systems;distance measurement using radio frequency identification technology;intelligent advisory systems and information technology support for decision making in tourism;morphological processing of videostream frames binary masks;algorithms for software clustering and modularization;cryptographic information protection using extended finite fields;image segmentation via X-means under overlapping classes;methods of protection document formed from latent element located by fractals;e-science: new paradigms, system integration and scientific research organization;flexible 2D membership functions for images filtering using fuzzy peer group approach;and combinatorial mathematical model and decision strategy for one-to-one pickup and delivery problem with 3d loading constraints.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Big/little deep neural network for ultra low power inference 15

Big/little deep neural network for ultra low power inference

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Eunhyeok Park Dongyoung Kim Soobeom Kim Yong-Deok Kim Gunhee Kim Sungroh Yoon Sungjoo Yoo Computing Memory Architecture Lab Seoul National University Device Solutions Samsung Electronics Software R&D Center Vision and Learning Lab Seoul National University Advanced Computing Lab Seoul National University

ISBN: (纸本)9781467383219

Deep neural networks (DNNs) have recently proved their effectiveness in complex data analyses such as object/speech recognition. As their applications are being expanded to mobile devices, their energy efficiencies are becoming critical. In this paper, we propose a novel concept called big/LITTLE DNN (BL-DNN) which significantly reduces energy consumption required for DNN execution at a negligible loss of inference accuracy. The BL-DNN consists of a little DNN (consuming low energy) and a full-fledged big DNN. In order to reduce energy consumption, the BL-DNN aims at avoiding the execution of the big DNN whenever possible. The key idea for this goal is to execute the little DNN first for inference (without big DNN execution) and simply use its result as the final inference result as long as the result is estimated to be accurate. On the other hand, if the result from the little DNN is not considered to be accurate, the big DNN is executed to give the final inference result. This approach reduces the total energy consumption by obtaining the inference result only with the little, energy-efficient DNN in most cases, while maintaining the similar level of inference accuracy through selectively utilizing the big DNN execution. We present design-time and runtime methods to control the execution of big DNN under a trade-off between energy consumption and inference accuracy. Experiments with state-of-the-art DNNs for ImageNet and MNIST show that our proposed BL-DNN can offer up to 53.7% (ImageNet) and 94.1% (MNIST) reductions in energy consumption at a loss of 0.90% (ImageNet) and 0.12% (MNIST) in inference accuracy, respectively.

关键词： Energy consumption Accuracy Biological neural networks hardware Energy efficiency Neurons Memory management

来源：评论

学校读者我要写书评

暂无评论

Development and application of remote laboratory for embedded systems design

Development and application of remote laboratory for embedde...

引用

international conference on Remote Engineering and Virtual Instrumentation (REV)

作者： Parkhomenko Anzhelika Gladkova Olga Eugene Ivanov Aleksandr Sokolyanskii Sergey Kurson Software Tools Department Zaporizhzhya National Technical University Zaporizhzhya Ukraine

This paper devoted to Embedded systems' hardware-software codesign and an overview of approach based on using ready platforms. Comparable analysis of well-known platforms from different vendors is given. Application of remote laboratories of the embedded system rapid prototyping was offered. Remote lab architecture, set of experiments and use case scenario are described. Proposed approach improves the current state of the art in the area of embedded systems design allowing to accelerate stages of hardware-software integration and testing.

关键词： Embedded systems hardware Remote laboratories Servers Microcontrollers software tools

来源：评论

学校读者我要写书评

暂无评论

How to improve the space utilization of dedup-based PCM storage devices? 15

How to improve the space utilization of dedup-based PCM stor...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Chun-Ta Lin Yuan-Hao Chang Tei-Wei Kuo Hung-Sheng Chang Hsiang-Pang Li Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C. Institute of Information Science Academia Sinica Taipei Taiwan R.O.C. Research Center for Information Technology Innovation Academia Sinica Taipei Taiwan R.O.C. Macronix International Co. Ltd. Emerging System Lab. Hsinchu Taiwan R.O.C.

ISBN: (纸本)9781467383219

There is a growing demand to introduce more and more intelligence to storage devices in recent years, especially with the rapid increasing of hardware computing power. This paper targets on essential design issues in space utilization for dedup-based non-volatile phase-change memory (PCM). We explore the adoption of data duplication techniques to reduce potential data duplicates over PCM storage devices to provide more storage space than the physical storage space does. Among various data deduplication techniques, variable-sized chunking is considered in less cost-effective PCM-based storage devices because variable-sized chunking has better data deduplication capability than fixed-sized chunking. However, in a typical system architecture, data are written or updated in the fixed management units (e.g., LBAs). Thus, to ultimately improve the space utilization of PCM-based storage device, the technical problem falls on (1) how to map fixed-sized LBAs to variable-sized chunks and (2) how to efficiently manage (i.e., allocated and deallocate) free PCM storage space for variable-sized chunks. In this work, we propose a free space manager, called container-based space manager, to resolve the above two issues by exploiting the fact that (1) a storage system initially has more free space to relax the complexity on space management and (2) the space optimization of a storage system can grow with the time when it contains more and more data. The proposed design is evaluated over popular benchmarks, for which we have very encouraging results.

关键词： Phase change materials Power capacitors Performance evaluation Ash Computer architecture Random access memory Media

来源：评论

学校读者我要写书评

暂无评论

High-level Synthesizable Dataflow MapReduce Accelerator for FPGA-coupled Data Centers 15

High-level Synthesizable Dataflow MapReduce Accelerator for ...

引用

international conference on Embedded Computer systems Architectures Modeling and Simulation

作者： Diamantopoulos, Dionysios Kachris, Christoforos Natl Tech Univ Athens Sch Elect & Comp Engn GR-10682 Athens Greece Democritus Univ Thrace Dept Elect & Comp Engn Xanthi Greece

ISBN: (纸本)9781467373111

Manipulating big-data entries of emerging server workloads requires a design paradigm shift towards more aggressive system-level architecture solutions. From software perspective, the MapReduce framework is a prominent parallel data processing tool as the volume of data to analyze grows rapidly. FPGAs can be used to accelerate the processing of data and reduce significantly the power consumption. However, FPGAs have not been deployed in data centers due to the high programming complexity of hardware. In this paper we present HLSMapReduceFlow, i.e. a novel reconfigurable MapReduce accelerator that can be scaled-up to data centers and it can speedup the processing of Map computation kernels, while promising minimum energy footprint and high programming efficiency due to the use of HLS. We propose the complete decoupling of MapReduce's tasks data-paths to distinct buses, accessed from individual processing engines. Such a dataflow approach implies a holistic C/C++ to RTL domain-level MapReduce transition. In this work, we further extent HLS tools, with systematic source to-source code annotation of HLS optimization directives, by adding as a state-of-art system-level implementation toolfiow. The proposed architecture is implemented, mapped and evaluated to a Virtex-7 FPGA and shows that the proposed scheme can achieve up to 43 x overall throughput improvement in MapReduce applications, while offering two orders of magnitude power/energy improvements compared to a high-end multi-core processor.

关键词： MapReduce hardware accelerator High-Level synthesis Reconfigurable computing Dataflow computing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共156页 << < 31 32 33 34 35 36 37 38 39 40 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：