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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1554 条记录，以下是381-390 订阅

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Accelerating full-system simulation and app analysis through focused multi-granularity profiling

Accelerating full-system simulation and app analysis through...

引用

Electronic system Level synthesis conference (ESLsyn)

作者： Tzu-Hsiang Su Wei-Shan Wu Chen-Te Chou Yuan-Chun Cheng Meng-Ting Tsai Tien-Fu Chen Dept. of CS National Chiao Tung University Taiwan R.O.C. Macronix International Co. Ltd.

Faced with the rapid divergence of hardware used on embedded devices, there is a need for a tool that can efficiently assist with hardware/software co-design and architecture verification. Speeding up those ESL phases greatly reduces the length of development periods. To address this issue, our work implements a novel multi-granularity tracer for Android's simulator to provide ESL hardware design performance analysis and verification. In addition, we propose a flexible ESL module interface for system hardware designers to explore new hardware components via simple modules. Our work also enables software developers to identify performance bottleneck and assess software performance of new hardware components. Our case studies and experimental results show that our multi-granularity Android tracer can strip away irrelevant information to shave time off the architecture development period.

关键词： Instruments hardware Androids Humanoid robots Generators Virtual machining Smart phones

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APECS code synthesis: Extending ocarina for multi-threaded code synthesis from AADL models for Safety Critical applications

APECS code synthesis: Extending ocarina for multi-threaded c...

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IEEE international conference on Networking, Sensing and Control

作者： Matthew Anderson Sandeep K. Shukla Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA

For Safety Critical CPS applications, Architecture Analysis and Design Language (AADL) can provide a framework for formally modeling end-to-end Cyber Physical systems (CPS). Such a model includes hardware platform model, software architecture model, the real-time bounds on software and hardware components. An AADL model of the system allows early formal analysis of real-time schedulability, end-to-end performance, power, memory requirements and correctness. Multiple tool support for AADL modeling and analysis exists, including software code generator, which glues together software components declared in the software architecture model. Ocarina is one such tool for software generation but it requires that the modeler provides the subprogram code in C/C++ or Ada. For correct-by-construction code synthesis, it is ideal to eliminate manually written code, and instead of using Ocarina as a glue code generator, using it for complete code synthesis from formal models. Support for Esterel and Lustre based specification of subprograms already have been attempted, but they usually specify specific subprogram elements, and the specific code generators are invoked to synthesis C/C++ code and then Ocarina glues them together based on the architectural constraints specified in the AADL model. This means that in a multi-threaded or multi-process software architecture, we still have to maneuver to get correct synchronization code. Moreover, if the granularity of code synthesis is at the function or subprogram level, we cannot gain much towards the goal of correct-by-construction synthesis and we believe that taking advantage of polychronous modeling and code synthesis would be ideal to achieve that goal. In this work, we show how to extend the Ocarina code generator to work with our Polychronous modeling and code synthesis solution to obtain multi-threaded code, improving the code-synthesis granularity from subprograms to processes while guaranteeing the implementation correctness.

关键词： Analytical models Process control Manuals Generators Synchronization Standards Context

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An Equivalence Checker for hardware-Dependent Embedded system software

An Equivalence Checker for Hardware-Dependent Embedded Syste...

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11th IEEE/ACM international conference on Formal Methods and Models for codesign (MEMOCODE)

作者： Villarraga, Carlos Schmidt, Bernard Bormann, Joerg Bartsch, Christian Stoffel, Dominik Kunz, Wolfgang U Kaiserslautern Dept Elect & Comp Eng Kaiserslautern Germany

ISBN: (纸本)9781479909032

This paper presents a novel approach to formally prove the equivalence of low-level hardware-dependent programs. Inspired by hardware verification techniques, a software miter is created that compares the behaviors of two programs, taking into account the interfaces between the software and the hardware environments. Two programs are considered equivalent if they produce the same outputs for the same input assignments and also exhibit the same sequences of interactions with the relevant hardware peripherals. This motivates a hardware-dependent computational model combining a path-oriented program view, as is common in hardware-independent software verification, with a structural hardware representation of the program's computation. Experimental results show the effectiveness of the proposed technique for industrial low-level software in important equivalence checking scenarios such as code porting and automated/manual code transformations.

关键词： Cosine transforms

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Splitting functions into single-entry regions

Splitting functions into single-entry regions

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proceedings of the international conference on Compilers, Architectures and synthesis for Embedded systems (CASES)

作者： Stefan Hepp Florian Brandner Institute of Computer Languages Vienna University of Technology Department ENSTA ParisTech Computer Science and System Engineering

As the performance requirements of today's real-time systems are on the rise, system engineers are increasingly forced to optimize and tune the execution time of real-time software. Apart from usual optimizations targeting the average-case performance of a program, the worst-case execution time bound (WCET) delivered by program analysis tools often has to be improved to meet all the deadlines and ensure a safe operation of the entire system. Modern computer architectures pose a significant challenge to this task due to their high complexity. Out-of-order execution, speculation, caches, buffers, and branch predictors highly depend on the execution history and are thus difficult to analyze precisely for WCET analysis tools. Time-predictable computer architectures overcome this problems by specifically designed hardware components that are amenable to static program analysis. A recently proposed alternative for caching executable code, i.e., instructions, is the so-called method cache. Instead of a traditional block-based cache design, the method cache operates on larger code blocks under the control of the compiler. Due to its design, the analysis of the method cache is simplified. At the same time, such a system now highly depends on the compiler and its ability to form suitable code blocks for caching. We propose a simple function splitting technique that derives a suitable partitioning of the basic blocks in a program, targeting the method cache of the time-predictable processor Patmos. Our approach exploits dominance properties to form code regions respecting the method cache's parameters as well as constraints of Patmos' instruction set architecture. Experimental results show that the method cache can be competitive with typical instruction cache configurations given the right splitting.

关键词： hardware Real-time systems Computer architecture Complexity theory software Partitioning algorithms Standards

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MEMOCODE 2013 hardware/software Co-design Contest: Stereo Matching

MEMOCODE 2013 Hardware/Software Co-design Contest: Stereo Ma...

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11th IEEE/ACM international conference on Formal Methods and Models for codesign (MEMOCODE)

作者： Nurvitadhi, Eriko Intel Sci & Technol Ctr Embedded Comp Pittsburgh PA 15213 USA

ISBN: (纸本)9781479909032

The MEMOCODE 2013 design contest problem is matching. Given a stereo image pair (i. e., a left image and right image), the challenge is to infer the depth information e., third dimension) for each pixel in the image utilizing belief algorithm. Contestants were given a month to a fast and/or cost-effective system for stereo matching. a total of eight participating teams, three winners were based on pure-performance and cost-adjustedmetrics, taking into consideration inference achieved by their design solutions. The winning teams hierarchical belief propagation algorithm on Intel multisystems, streaming tree-reweighted message passing (TRWalgorithm on Convey HC-1 FPGA platform, and tile-based propagation algorithm on Nvidia GTX 680 GPU platform.

关键词： stereo matching belief propagation hardware-software codesign multicore FPGAs GPUs

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APECS: An AADL and Polychrony based Embedded Computing system Design Environment with an Elevator Control Case Study

APECS: An AADL and Polychrony based Embedded Computing Syste...

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11th IEEE/ACM international conference on Formal Methods and Models for codesign (MEMOCODE)

作者： Anderson, Matthew Shukla, Sandeep K. Virginia Polytech Inst & State Univ Bradley Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)9781479909032

Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for capturing an entire distributed platform architecture (hardware components, protocols, and software architecture annotated with properties including real-time measures). The software architecture captures the location and structure of processes, threads, and the data and control flow specifications. The behavior of the processes/threads/subprograms are provided via a native state machine language or via a behavioral annex. Schedulability, performance, and other system level properties can be analyzed using various tools. Even code synthesis - targeting the formally described platform components and middleware can be enabled if the threads/processes can be behaviorally specified. In this paper, we describe our methodology and a design environment both named APECS. APECS is meant for enabling an end-to-end distributed real-time embedded system design which integrates a number of existing tools, and our own polychronous language based specification language MRICDF, and the corresponding synthesis methodology. While the environment is in an advanced stage of development, we illustrate the architecture of the design environment, and illustrate the methodology through a non-trivial case study. The case study uses APECS methodology and tools in developing the distributed control for a 4 bank elevator system in a 5 story building. We posit this paper as a methodology and tool paper and it is written in a tutorial spirit rather than a paper describing new theories or algorithms.

关键词： software architecture designing of environment avionics Developmental stages elevator control Environments embedded system design Building construction ARCHITECTURE Embedded computing Case studies paper methodology Middleware Language

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hardware software Co-design of Pipelined Instruction Decoder in system Emulation

Hardware Software Co-design of Pipelined Instruction Decoder...

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2013 IEEE 4th international conference on software Engineering and Service Science

作者： Sichun Zhang Liehui Jiang Xiaojuan Zhang Xiaolong Hu China National Digital Switching System Engineering and Technological Research Center

ISBN: (纸本)9781467349994

system emulation based on dynamic binary translation can solve the problems of compatibility between heterogeneous *** on this field is mostly based on software,the efficiency is very low and restricting the performance of X86 system *** paper presents hardware software codesign of pipelined instruction decoder to avoid the inefficiency of system emulator based on *** decoder is controlled by the software unit and supported by the hardware unit via *** to system emulator based on software,the average speedup of pipelined instruction decoder achieves 5.2 and there is a significant performance improvement on system emulation.

关键词： pipelined stages co-design instruction decoder length of instruction system emulation

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hardware neural network accelerators

Hardware neural network accelerators

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Temam, O. INRIA Saclay France

""Because of increasingly stringent energy constraints (e.g., Dark Silicon, there is a growing consensus in the community that we may be moving towards heterogeneous multi-core architectures, composed of a m... 详细信息

ISBN: (纸本)9781479914173

关键词： application specific integrated circuits fault tolerant computing graphics processing units learning (artificial intelligence) multiprocessing systems neural nets parallel architectures power aware computing

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system level synthesis of hardware for DSP applications using pre-characterized function implementations

System level synthesis of hardware for DSP applications usin...

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Li, Shuo Farahini, Nasim Hemani, Ahmed Rosvall, Kathrin Sander, Ingo ES/ICT/KTH Forum 120 SE-164 40 Kista Sweden

ISBN: (纸本)9781479914173

SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results. © 2013 IEEE.

关键词： Data transfer

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Automatic refinement of requirements for verification throughout the SoC design flow

Automatic refinement of requirements for verification throug...

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Pierre, Laurence Bel Hadj Amor, Zeineb TIMA Laboratory CNRS-INPG-UJF 46 Avenue Félix Viallet 38031 Grenoble cedex France

ISBN: (纸本)9781479914173

This paper focuses on the verification of requirements for hardware/software systems on chip (SoC's) along the design flow. In the early stages of this flow, the Electronic system Level (ESL) description style, and languages such as systemC TLM, enable high-level debugging of the SoC functionality. In the last stages, hardware blocks become RTL or gate level (VHDL or Verilog) descriptions. We have developed two autonomous Assertion-Based Verification (ABV) solutions, for systemC TLM platforms and for VHDL/Verilog IP blocks: designs are automatically instrumented with ad hoc property checkers produced from requirements formalized as PSL assertions. Furthermore, for a comprehensive and seamless verification flow, analogous requirements should be verifiable before and after ESL-to-RTL hardware refinement. This requires the transformation of ESL assertions into their counterparts at the RT level. This paper discusses this issue and proposes a first set of transformation rules for the automatic refinement of PSL assertions from the system level to the signal level. Properties of an industrial case study are used as illustrative examples. © 2013 IEEE.

关键词： system-on-chip

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