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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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CMSM: An efficient and effective code management for software managed multicores

CMSM: An efficient and effective code management for softwar...

引用

11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Bai, Ke Lu, Jing Shrivastava, Aviral Holton, Bryce Compiler Microarchitecture Laboratory Arizona State University Tempe AZ 85287 United States

ISBN: (纸本)9781479914173

As we scale the number of cores in a multicore processor, scaling the memory hierarchy is a major challenge. software Managed Multicore (SMM) architectures are one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory. If all the code and data of the task mapped to a core do not fit on its local scratchpad memory, then explicit code and data management is required. In this paper, we solve the problem of efficiently managing code on an SMM architecture. We extend the state of the art by: i) correctly calculating the code management overhead, ii) even in the presence of branches in the task, and iii) developing a heuristic CMSM (Code Mapping for software Managed multicores) that results in efficient code management execution on the local scratchpad memory. Our experimental results collected after executing applications from MiBench suite [1] on the Cell SPEs (Cell is an SMM architecture) [2], demonstrate that correct management cost calculation and branch consideration can improve performance by 12%. Our heuristic CMSM can reduce runtime in more than 80% of the cases, and by up to 20% on our set of benchmarks. © 2013 IEEE.

关键词： Embedded systems

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VarEMU: An emulation testbed for variability-aware software

VarEMU: An emulation testbed for variability-aware software

引用

11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Wanner, Lucas Elmalaki, Salma Lai, Liangzhen Gupta, Puneet Srivastava, Mani University of California Los Angeles CA United States

ISBN: (纸本)9781479914173

Modern integrated circuits, fabricated in nanometer technologies, suffer from significant power/performance variation across-chip, chip-to-chip and over time due to aging and ambient fluctuations. Furthermore, several existing and emerging reliability loss mechanisms have caused increased transient, intermittent and permanent failure rates. While this variability has been typically addressed by process, device and circuit designers, there has been a recent push towards sensing and adapting to variability in the various layers of software. Current hardware platforms, however, typically lack variability sensing capabilities. Even if sensing capabilities were available, evaluating variability-aware software techniques across a significant number of hardware samples would prove exceedingly costly and time consuming. We introduce VarEMU, an extension to the QEMU virtual machine monitor that serves as a framework for the evaluation of variability-aware software techniques. VarEMU provides users with the means to emulate variations in power consumption and in fault characteristics and to sense and adapt to these variations in software. Through the use (and dynamic change) of parameters in a power model, users can create virtual machines that feature both static and dynamic variations in power consumption. Faults may be injected before or after, or completely replace the execution of any instruction. Power consumption and susceptibility to faults are also subject to dynamic change according to an aging model. A software stack for VarEMU features precise control over faults and provides virtual energy monitors to the operating system and processes. This allows users to precisely quantify and evaluate the effects of variations on individual applications. We show how VarEMU tracks energy consumption according to variation-aware power and aging models and give examples of how it may be used to quantify how faults in instruction execution affect applications. © 2013 IEEE.

关键词： Electric power utilization

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PvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment

PvFPGA: Accessing an FPGA-based hardware accelerator in a pa...

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Wang, Wei Bolic, Miodrag Parri, Jonathan Computer Architecture Research Group University of Ottawa Ottawa ON Canada

ISBN: (纸本)9781479914173

In this paper we present pvFPGA, the first system design solution for virtualizing an FPGA-based hardware accelerator on the x86 platform. Our design adopts the Xen virtual machine monitor (VMM) to build a paravirtualized environment, and a Xilinx Virtex-6 as an FPGA accelerator. The accelerator communicates with the x86 server via PCI Express (PCIe). In comparison to the recent accelerator virtualization solutions which primarily intercept and redirect API calls to the hosted or privileged domain's user space, pvFPGA virtualizes an FPGA accelerator directly at the lower device driver level. This gives rise to higher efficiency and lower overhead. In pvFPGA, each unprivileged domain allocates a shared data pool for both user-kernel and inter-domain data transfer. In addition, we propose a new component, the coprovisor, which enables multiple domains to simultaneously access an FPGA accelerator. The experimental results have shown that 1) pvFPGA achieves close-to-zero overhead compared to accessing the FPGA accelerator without the VMM layer, 2) the FPGA accelerator is successfully shared by multiple domains, and 3) distributing different maximum data transfer bandwidths to different domains is achieved by regulating the size of the shared data pool at the split driver loading time. © 2013 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Designing a residential hybrid electrical energy storage system based on the energy buffering strategy

Designing a residential hybrid electrical energy storage sys...

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Zhu, Di Yue, Siyu Wang, Yanzhi Kim, Younghyun Chang, Naehyuck Pedram, Massoud University of Southern California CA United States Seoul National University Korea Republic of

ISBN: (纸本)9781479914173

Due to severe variation in load demand over time, utility companies generally raise electrical energy price during periods of high load demand. A grid-connected hybrid electrical energy storage (HEES) system can help residential users lower their electric bills by storing energy during low-price hours and releasing the stored energy during high-price hours. A HEES system consists of different types of electrical energy storage (EES) elements, utilizing the benefits of each type while hiding their weaknesses. This paper presents a residential energy management system to maximize the annual profits on residential electric bills, based on a HEES system comprised of a lead-acid battery bank as the main storage bank and a Li-ion battery bank as the energy buffer. We first derive the optimal daily energy management policy based on energy buffering to minimize the daily energy cost. Next, we find the near-optimal design specifications of the energy management system, aiming at maximizing the amortized annual profits under practical constraints. We show that this system achieves averagely 11.10% more profits compared to the none-buffering HEES system. © 2013 IEEE.

关键词： Energy management

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A reconfigurable real-time SDRAM controller for mixed time-criticality systems

A reconfigurable real-time SDRAM controller for mixed time-c...

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Goossens, Sven Kuijsten, Jasper Akesson, Benny Goossens, Kees Eindhoven University of Technology Netherlands

ISBN: (纸本)9781479914173

Verifying real-time requirements of applications is increasingly complex on modern systems-on-Chips (SoCs). More applications are integrated into one system due to power, area and cost constraints. Resource sharing makes their timing behavior interdependent, and as a result the verification complexity increases exponentially with the number of applications. Predictable and composable virtual platforms solve this problem by enabling verification in isolation, but designing SoC resources suitable to host such platforms is challenging. This paper focuses on a reconfigurable SDRAM controller for predictable and composable virtual platforms. The main contributions are: 1) A run-time reconfigurable SDRAM controller architecture, which allows trade-offs between guaranteed bandwidth, response time and power. 2) A methodology for offering composable service to memory clients, by means of composable memory patterns. 3) A reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level systemC model, and in synthesizable VHDL for use on an FPGA. © 2013 IEEE.

关键词： system-on-chip

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Tutorials

Tutorials

引用

international conference on hardware/software codesign and system synthesis (CODES)

Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.

关键词： Embedded systems Program processors Unified modeling language Computer architecture hardware Reliability

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Improving polyhedral code generation for high-level synthesis

Improving polyhedral code generation for high-level synthesi...

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11th ACM/IEEE international conference on hardware/software codesign and system synthesis, CODES+ISSS 2013

作者： Zuo, Wei Li, Peng Chen, Deming Pouchet, Louis-Nöel Zhong, Shunan Cong, Jason Beijing Institute of Technology China Peking University China PKU UCLA Joint Research Institution for Science and Engineering United States University of California Los Angeles CA United States University of Illinois Urbana-Champaign IL United States

ISBN: (纸本)9781479914173

High-level synthesis (HLS) tools are now capable of generating high-quality RTL codes for a number of programs. Nevertheless, for best performance aggressive program transformations are still required to exploit data reuse and enable communication/computation overlap. The polyhedral compilation framework has shown great promise in this area with the development of HLS-specific polyhedral transformation techniques and tools. However, all these techniques rely on polyhedral code generation to translate a schedule for the program's operations into an actual C code that is input to the HLS tool. In this work we study the changes to the state-of-the-art polyhedral code generator CLooG which are required to tailor it for HLS purposes. In particular, we develop various techniques to significantly improve resource utilization on the FPGA. We also develop a complete technique geared towards effective code generation of rectangularly tiled code, leading to further improvements in resource utilization. We demonstrate our techniques on a collection of affine benchmarks, reducing by 2x on average (up to 10x) the area used after high-level synthesis. © 2013 IEEE.

关键词： High level synthesis

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Bitwidth-Optimized hardware Accelerators with software Fallback

Bitwidth-Optimized Hardware Accelerators with Software Fallb...

引用

12th international conference on Field-Programmable Technology (FPT)

作者： Klimovic, Ana Anderson, Jason H. Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781479921980;9781479921997

We propose the high-level synthesis of an FPGA-based hybrid computing system, where the implementations of compute-intensive functions are available in both software, and as hardware accelerators. The accelerators are optimized to handle common-case inputs, as opposed to worst-case inputs, allowing accelerator area to be reduced by 28%, on average, while retaining the majority of performance advantages associated with a hardware versus software implementation. When inputs exceed the range that the hardware accelerators can handle, a software fallback is automatically triggered. Optimization of the accelerator area is achieved by reducing datapath widths based on application profiling of variable ranges in software (under typical datasets). The selected widths are passed to a high-level synthesis tool which generates the accelerator for a given function. The optimized accelerators with software fallback capability are generated automatically by our framework, with minimal user intervention. Our study explores the trade-offs of delay and area for benchmarks implemented on an Altera Cyclone II FPGA.

关键词： hardware accelerator computer software high level synthesis Accelerators computer programs software implementation BENCHMARKS variable range AUTOMATIC Computer hardware

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Reliable Pre-scheduling Delay Estimation for hardware/software partitioning

Reliable Pre-scheduling Delay Estimation for Hardware/Softwa...

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IEEE 56th international Midwest Symposium on Circuits and systems (MWSCAS)

作者： Hassan, Rania O. Abdelhalim, M. B. Habib, S. E. -D. Cairo Univ Elect & Commun Engn Dept Giza Egypt CCIT AASTMT Cairo Egypt

ISBN: (纸本)9781479900664

hardware and software co-design has become one of the main methodologies in modern embedded systems. The partitioning step, i.e. to decide which components of the system should be implemented in hardware and which ones in software, is the most important step in the embedded systems. Since the costs and delays of the final design strongly depend on partitioning results, there is a need to get an accurate estimate for hardware area, delay and power. However, accurate delay estimation methods are slow as they need a scheduling step. In this paper, we propose a reliable delay estimation method to be used within the partitioning step prior to the scheduling step.

关键词： hardware/software Co-design hardware/software Partitioning Control-Data Flow Graphs FPGAs High-level synthesis Design Space Exploration MPSOC

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A Prototyping system for hardware Distributed Objects with Diversity of Programming Languages

A Prototyping System for Hardware Distributed Objects with D...

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12th international conference on Field-Programmable Technology (FPT)

作者： Ohkawa, Takeshi Yokota, Takashi Ootsu, Kanemitsu Utsunomiya Univ Grad Sch Engn Utsunomiya Tochigi 321 Japan

ISBN: (纸本)9781479921980;9781479921997

A prototyping system for hardware distributed objects using a hardwired ORB (Object Request Broker) protocol processing engine was implemented on Xilinx Zynq-7000 platform;by which a circuit IP on an FPGA can be operated from application software on Linux/ARM processor through an object-oriented method call. The proposed framework increases controllability and design-productivity on FPGA-based systems. A developer can define an object-oriented interface for a circuit IP in an FPGA, and implement the control sequence part using JavaRock Java-to-HDL synthesizer. By the conformance to the standard CORBA (Common Object Request Broker Architecture) protocol, circuit IPs in an FPGA can be handled through object-oriented interface from diversity of programing languages;like C++, Java, Python and so on. The round trip delay performance measurement of the prototype system was done on Xillybus FIFO interface channel.

关键词： high-level synthesis languages and modeling techniques intellectual property core based design hardware/software co-design embedded applications

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