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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1556 条记录，以下是431-440 订阅

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A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters 13

A variability-aware OpenMP environment for efficient executi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Abbas Rahimi Andrea Marongiu Rajesh K. Gupta Luca Benini Department of Computer Science and Engineering UC San Diego La Jolla CA USA Dipartimento di Ingegneria dell'Energia Elettrica e dell'lnformazione Universita di Bologna Bologna Italy

ISBN: (纸本)9781479914173

We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floating-point units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, our programming and runtime environment also supports controlled approximate computation through a combination of design-time and runtime techniques. We provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately. We use a profiling technique to identify tolerable error significance and error rate thresholds in error-tolerant image processing applications. This information guides an application-driven hardware FPU synthesis and optimization design flow to generate efficient FPUs. At runtime, the scheduler utilizes FPV metadata and promotes FPUs to accurate mode, or demotes them to approximate mode depending upon the code region requirements. We demonstrate the effectiveness of our approach (in terms of energy savings) on a 16-core tightly-coupled cluster with eight shared-FPUs for both error-tolerant and general-purpose error-intolerant applications.

关键词： Pipelines Timing Approximation methods Registers Computer architecture Runtime software

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IVaM: Implicit variant modeling and management for automotive embedded systems 13

IVaM: Implicit variant modeling and management for automotiv...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sebastian Graf Michael Glaß Dominic Wintermann Jürgen Teich Christoph Lauer University of Erlangen-Nuremberg Germany Friedrich-Alexander-Universitat Erlangen-Nurnberg Erlangen Bayern DE AUDI AG Ingolstadt Germany

ISBN: (纸本)9781479914173

In this paper, we propose a graph-based approach for the modeling and efficient analysis of functional variants of a car's electric and electronic (E/E) architecture functionality by combining local technical expert knowledge with global business knowledge. Starting with a variants system specification including a set of task graphs, linear constraints on binary variables are specified for their alternative selection as well as the selection of groups of alternatives called application groups. These constraints may stem from a certain domain knowledge, e. g., entertainment or power train domain, or global constraints. The typically vast space of resulting possible combinations of different selections of alternative behaviors will be termed variant space and those satisfying the set of formulated constraints valid variants. An important result of this paper is that the set of variants, and especially the set of valid variants, do not need to be modeled or stored explicitly but rather implicitly. Nevertheless do we show that using state-of-the-art PB solver techniques, we may determine the set of valid variants very efficiently. Each of these valid variants may subsequently be used as a candidate for design space exploration (DSE) in order to optimize also the mapping of the corresponding task graph functionalities to a final optimized E/E architecture. A real-world case study is provided to demonstrate the capabilities and efficiency of the presented approach on implicit variant modeling and analysis.

关键词： Space exploration Computer architecture hardware software Automotive engineering Business Sensors

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Designing a residential hybrid electrical energy storage system based on the energy buffering strategy 13

Designing a residential hybrid electrical energy storage sys...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Di Zhu Siyu Yue Yanzhi Wang Younghyun Kim Naehyuck Chang Massoud Pedram University of Southern California CA USA Seoul National University Korea

ISBN: (纸本)9781479914173

Due to severe variation in load demand over time, utility companies generally raise electrical energy price during periods of high load demand. A grid-connected hybrid electrical energy storage (HEES) system can help residential users lower their electric bills by storing energy during low-price hours and releasing the stored energy during high-price hours. A HEES system consists of different types of electrical energy storage (EES) elements, utilizing the benefits of each type while hiding their weaknesses. This paper presents a residential energy management system to maximize the annual profits on residential electric bills, based on a HEES system comprised of a lead-acid battery bank as the main storage bank and a Li-ion battery bank as the energy buffer. We first derive the optimal daily energy management policy based on energy buffering to minimize the daily energy cost. Next, we find the near-optimal design specifications of the energy management system, aiming at maximizing the amortized annual profits under practical constraints. We show that this system achieves averagely 11.10% more profits compared to the none-buffering HEES system.

关键词： Batteries Lead Discharges (electric) Pricing Energy management Supercapacitors

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An Automated Flow for the High Level synthesis of Coarse Grained Parallel Applications

An Automated Flow for the High Level Synthesis of Coarse Gra...

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12th international conference on Field-Programmable Technology (FPT)

作者： Castellana, Vito Giovanni Ferrandi, Fabrizio Politecn Milan DEIB I-20133 Milan Italy

ISBN: (纸本)9781479921980;9781479921997

High Level synthesis (HLS) provides a way to significantly enhance the productivity of embedded system designers, by enabling the automatic or semiautomatic generation of hardware accelerators starting from high level descriptions with (usually software) programming languages. Typical HLS approaches build a centralized Finite State Machine (FSM) to control the generated datapath, performing the operations according to a pre-determined, static schedule. However, FSM-based approaches are only able to extract parallelism within a single execution flow. In the presence of coarse grained parallelism, in the form of concurrent function calls or parallel control structures, they either serialize all the operations, or build excessively complex controllers, aiming at executing as many operation as possible in a single control step (i.e., they try to extract as much instruction level parallelism as possible). The resulting controllers occupy an excessive amount of area or lead to very low operating frequencies. In this paper we propose a methodology for the HLS of accelerators supporting parallel execution and dynamic scheduling. The approach exploits an adaptive distributed controller, composed of a set of communicating elements associated with each operation. This controller design enables supporting multiple concurrent execution flows, thus increasing parallelism exploitation beyond instruction level parallelism. The approach also supports variable latency operations, such as memory accesses and speculative operations. We apply our methodology on a set of typical HLS benchmarks, and demonstrate valuable speed ups with limited area overheads with respect to conventional FSM-based flows.

关键词： parallelism hue lightness saturation Synclitism high level synthesis parallel execution executive stream Surgery hardware accelerator parallel control Accelerators Controllers controller design

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Insect Type MEMS Micro Robot Controlled by CMOS IC of hardware Neural Networks 12

Insect Type MEMS Micro Robot Controlled by CMOS IC of Hardwa...

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12th European conference on the synthesis and Simulation of Living systems: Advances in Artificial Life, ECAL 2013

作者： Takato, M. Yamasaki, S. Takahama, S. Tanida, J. Saito, K. Uchikoba, F. Precision Machinery Engineering Graduate School of Science and Technology Nihon University Japan Dept. of Precision Machinery Engineering Collage of Science and Technology Nihon University Japan

ISBN: (纸本)9780262317092

This paper describes insect type micro robots controlled by a CMOS IC of hardware neural networks. The micro robot is fabricated by the micro electro mechanical systems (MEMS) technology using a silicon wafer, and the actuator is composed of artificial muscle wires on the basis of shape memory alloy. Insect-like walking is achieved by link mechanisms that transform the actuator s rotational motion to locomotive motion. The CMOS IC generates the driving waveform of the micro robot and realizes insect-like walking. The hardware neural networks are built as cell body models and inhibitory synaptic models. The output signal ports of the hardware neural networks are connected to the artificial-muscle-wire-driving circuit. This robot system does not require specialized software programs and A/D converters. The developed neural networks are composed of self-functioning, interconnected plural unit neurons. For proper driving, each neuron in the developed neural network control must be synchronized, as occurs in the neural networks of living organisms. In this study, the motion of the MEMS micro robot is controlled by non-synchronization and anti-phase synchronization driving waveforms. When the nonsynchronization driving waveform is input, the micro robot ceases walking motion, but resumes walking upon receipt of the anti-phase synchronization driving waveform. The sideways, endways, and height dimensions of the fabricated micro robot are 4.0 mm, 2.7 mm and 2.5 mm, respectively. The obtained locomotion speed is 26.4 mm/min and the step width is 0.88 mm. © 2013 proceedings of the 12th European conference on the synthesis and Simulation of Living systems: Advances in Artificial Life, ECAL 2013. All rights reserved.

关键词： Neural networks

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An equivalence checker for hardware-dependent embedded system software 13

An equivalence checker for hardware-dependent embedded syste...

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proceedings of the Eleventh ACM/IEEE international conference on Formal Methods and Models for codesign

ISBN: (纸本)9781479909056

This paper presents a novel approach to formally prove the equivalence of low-level hardware-dependent programs. Inspired by hardware verification techniques, a software miter is created that compares the behaviors of two programs, taking into account the interfaces between the software and the hardware environments. Two programs are considered equivalent if they produce the same outputs for the same input assignments and also exhibit the same sequences of interactions with the relevant hardware peripherals. This motivates a hardware-dependent computational model combining a path-oriented program view, as is common in hardware-independent software verification, with a structural hardware representation of the program's computation. Experimental results show the effectiveness of the proposed technique for industrial low-level software in important equivalence checking scenarios such as code porting and automated/manual code transformations.

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From software to accelerators with LegUp high-level synthesis

From software to accelerators with LegUp high-level synthesi...

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proceedings of the international conference on Compilers, Architectures and synthesis for Embedded systems (CASES)

作者： Andrew Canis Jongsok Choi Blair Fort Ruolong Lian Qijing Huang Nazanin Calagar Marcel Gort Jia Jun Qin Mark Aldham Tomasz Czajkowski Stephen Brown Jason Anderson ECE Department University of Toronto Toronto ON Canada

Embedded system designers can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators for an application can be difficult and time intensive. LegUp is an open-source high-level synthesis framework that simplifies the hardware accelerator design process [8]. With LegUp, a designer can start from an embedded application running on a processor and incrementally migrate portions of the program to hardware accelerators implemented on an FPGA. The final application then executes on an automatically-generated software/hardware coprocessor system. This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.

关键词： hardware software Field programmable gate arrays Pipeline processing Optimization Radiation detectors Clocks

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APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study

APECS: An AADL and polychrony based embedded computing syste...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Matthew Anderson Sandeep K. Shukla Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA

ISBN: (纸本)9781479909049

Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for capturing an entire distributed platform architecture (hardware components, protocols, and software architecture annotated with properties including real-time measures). The software architecture captures the location and structure of processes, threads, and the data and control flow specifications. The behavior of the processes/threads/subprograms are provided via a native state machine language or via a behavioral annex. Schedulability, performance, and other system level properties can be analyzed using various tools. Even code synthesis - targeting the formally described platform components and middleware can be enabled if the threads/processes can be behaviorally specified. In this paper, we describe our methodology and a design environment both named APECS. APECS is meant for enabling an end-to-end distributed real-time embedded system design which integrates a number of existing tools, and our own polychronous language based specification language MRICDF, and the corresponding synthesis methodology. While the environment is in an advanced stage of development, we illustrate the architecture of the design environment, and illustrate the methodology through a non-trivial case study. The case study uses APECS methodology and tools in developing the distributed control for a 4 bank elevator system in a 5 story building. We posit this paper as a methodology and tool paper and it is written in a tutorial spirit rather than a paper describing new theories or algorithms.

关键词： Analytical models Real-time systems Program processors Ports (Computers) Computer architecture Standards

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APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study 13

APECS: An AADL and polychrony based embedded computing syste...

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proceedings of the Eleventh ACM/IEEE international conference on Formal Methods and Models for codesign

ISBN: (纸本)9781479909056

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hardware supported adaptive data collection for networks on chip

Hardware supported adaptive data collection for networks on ...

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2013 IEEE 37th Annual Computer software and Applications conference, COMPSAC 2013

作者： Heisswolf, Jan Weichslgartner, Andreas Zaib, Aurang Konig, Ralf Wild, Thomas Herkersdorf, Andreas Teich, Jurgen Becker, Jurgen Karlsruhe Institute of Technology Germany University of Erlangen Nuremberg Germany Technical University Munich Germany

ISBN: (纸本)9780769549798

Managing future many-core architectures with hundreds of cores, running multiple applications in parallel, is very challenging. One of the major reasons is the communication overhead required to handle such a large system. Distributed management is proposed to reduce this overhead. The architecture is divided into regions which are managed separately. The instance managing the region and the applications running within the regions need to collect data for various reasons from time to time, e.g., to collect data for proper mapping decision, to synchronize tasks or to aggregate computation results. In this work, we propose and investigate different strategies for adaptive data collection in meshed Networks on Chip. The mechanisms can be used to collect data within regions, which are defined during run-time in respect of size and position. The mechanisms are investigated while considering delay, NoC utilization and implementation costs. The results show that the selection of the used mechanism depends on the requirements. synthesis results compare area overhead, timing impact and energy consumption. © 2013 IEEE.

关键词： Network-on-chip

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