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proceedings - 2012 IEEE 19th international conference and Workshops on Engineering of Computer-Based systems, ECBS 2012

Proceedings - 2012 IEEE 19th International Conference and Wo...

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2012 IEEE 19th international conference and Workshops on Engineering of Computer-Based systems, ECBS 2012

ISBN: (纸本)9780769546643

The proceedings contain 39 papers. The topics discussed include: complexity of a special deobfuscation problem;using template metaprogramming to enhance reuse in visitor-based model interpreters;automated software generation and hardware coprocessor synthesis for data-adaptable reconfigurable systems;modeling and verifying the ariadne protocol using CSP;model checking goal-oriented requirements for self-adaptive systems;using parameterized attributes to improve testing capabilities with domain-specific modeling languages;touch-screen stimulation for automated verification of touchscreen-based devices;simultaneous functionality verification system of multiple set-top boxes;an analytical review of process-centered software engineering environments;an architecture for safe and secure automation system devices and maintenance process;and beyond mainstream adoption: from agile software development to agile organizational change.

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An aircraft electric power testbed for validating automatically synthesized reactive control protocols

An aircraft electric power testbed for validating automatica...

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16th international conference on Hybrid systems: Computation and Control, HSCC 2013 - Part of CPSWeek 2013

作者： Rogersten, Robert Xu, Huan Ozay, Necmiye Topcu, Ufuk Murray, Richard M. KTH Royal Inst. of Tech. Sweden California Inst. of Tech. United States University of Pennsylvania United States

ISBN: (纸本)9781450315678

Modern aircraft increasingly rely on electric power for subsystems that have traditionally run on mechanical power. The complexity and safety-criticality of aircraft electric power systems have therefore increased, rendering the design of these systems more challenging. This work is motivated by the potential that correct-by-construction reactive controller synthesis tools may have in increasing the effectiveness of the electric power system design cycle. In particular, we have built an experimental hardware platform that captures some key elements of aircraft electric power systems within a simplified setting. We intend to use this platform for validating the applicability of theoretical advances in correct-by-construction control synthesis and for studying implementation-related challenges. We demonstrate a simple design workflow from formal specifications to autogenerated code that can run on software models and be used in hardware implementation. We show some preliminary results with different control architectures on the developed hardware testbed. Copyright © 2013 ACM.

关键词： Electric power system control

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2010 IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2010: Foreword

2010 IEEE/ACM/IFIP International Conference on Hardware/Soft...

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2010 IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2010 2010年 iii页

作者： Givargis, Tony Donlin, Adam

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Soft Errors: The hardware-software Interface 12

Soft Errors: The Hardware-Software Interface

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ACM international conference on hardware/software - codesign and system synthesis

作者： Kyoungwoo Lee Aviral Shrivastava Reiley Jeyapaul Yonsei University Seoul South Korea Arizona State University Phoenix USA

ISBN: (纸本)9781450314268

A recent report from the ITRS identifies soft errors, as one of the most important reliability challenges for the coming decades. Soft errors are transient errors caused by several effects e.g., voltage fluctuations, wire-cross talks, and cosmic particle strikes; and manifest as a temporary switch of the logic value of a transistor. While it is not possible to prove nor disprove that a certain error happened due to soft errors, several fiscal disasters e.g., Sun server crashes in 2000, and HP server crashes in 2005, have been attributed to soft errors. Industry has moved from the position of ignoring soft errors to adding design efforts for protection from them. For instance, in the recently announced nVIDIA's Fermi GPUs, the L1 cache, L2 cache and register files are ECC protected. Although the soft error rate is about once-per year today, it is expected to reach alarming levels of once-per-day in about a decade or two. Researchers are busy finding cost-effective solutions to protect computing devices from soft errors. This tutorial will attempt to cover the entire gamut of soft error protection techniques, but will particularly focus on the soft error mitigation techniques at the hardware/software interface. Much time will be spent on microarchitectural, compiler, and hybrid compiler-microarchitectural techniques for soft error mitigation. This tutorial will be particularly useful for budding researchers who are fascinated by soft errors, and want to explore this as their research direction. For such researchers, this tutorial will be a one-stop-shop to acquire knowledge of and analyze seminal research work in the field of soft error mitigation, at several design layers. For developers who have been working on soft errors at different levels, this will give them a picture of what can be done at other levels, so that they can provide complementary cross-layer protection. Finally, researchers and developers working on other aspects of system design can learn how soft

关键词： Soft error mitigation compiler microarchitectural techniques

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Optimized software mapping for advanced driver assistance systems

Optimized software mapping for advanced driver assistance sy...

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7th IEEE international Symposium on Industrial Embedded systems, SIES 2012

作者： Schönwald, Timo Viehl, Alexander Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 76131 Karlsruhe Germany Universität Tübingen Sand 13 72076 Tübingen Germany

ISBN: (纸本)9781467326841

In this paper, we present a novel approach for automated latency-optimized mapping of processes onto cores of NoC-based MPSoCs. During the mapping determination, the routing algorithm for packet-based communication is taken into account. The basic idea of the presented approach is the reduction of communication conflicts on the communication network links for reducing the overall communication latency and hence for increasing the total system performance. The presented approach is based on the idea of force-directed scheduling (FDS) from high-level synthesis. It maps the problem of conflict avoidance to forces for deriving an optimized process mapping. We present results obtained from two advanced driver assistance systems (ADAS), a traffic sign recognition and a depth map computation for a stereo camera system used for object recognition. As hardware platform we used a Tilera TILEPro64 processor system. © 2012 IEEE.

关键词： Mapping

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HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA

HLS-based fast design space exploration of ad hoc hardware a...

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conference on Design and Architectures for Signal and Image Processing

作者： Youenn Corre Van-Trinh Hoang Jean-Philippe Diguet Dominique Heller Loïc Lagadec Laboratory-STICC Université de Bretagne Sud Lorient France Laboratory-STICC Université de Bretagne Occidentale Brest France

Over the last decade many academic and industrial system synthesis and codesign tools have been proposed to designers. However most of these tools are based on IP Libraries but either these libraries are incomplete or are simply not adapted to the targets and constraints. It means that something important is missing when it comes to real implementations. We address this question in this paper and propose a flexible, fast and practical solution. We use high level synthesis (HLS) to obtain fast estimations of hardware accelerators that can then be embedded within the loop of a larger design space exploration flow. Once some solutions are selected they can be directly reuse to synthesise and produce real IPs. In this paper we present the approach and the tool as a key component of our heterogeneous multiprocessor synthesis framework.

关键词： hardware Field programmable gate arrays Computer architecture Estimation Libraries IP networks software

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NiosII custom instruction on FIR filter arithmetic

NiosII custom instruction on FIR filter arithmetic

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international conference on Modelling, Identification and Control (ICMIC)

作者： Ye Tian Yan Li Qiang Dong Institute of Optics and Precision Mechanics of CAS Xian China

According to the principle of FIR filter, we firstly design and simulate the model file with DSP Builder in the environment of Matlab/Simulink. Secondly, we transform this model file to VHDL source codes with Signal-Compiler and implement processes of analysis, synthesis and adaptation in Quartus II. At last, we create a SOPC system-NiosII, where FIR filter arithmetic can be generated to a custom instruction. Till now, the hardware-software co-design of FIR filter arithmetic has been completed.

关键词： Finite impulse response filter Digital signal processing hardware Mathematical model software IIR filters Field programmable gate arrays

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Linear processor array in DSP

Linear processor array in DSP

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international conference on Microelectronics, MIEL

作者： I. Ž. Milovanović M. K. Stojčev E. I. Milovanović T. R. Nikolić Faculty of Electronics Engineering Nis Serbia

This article presents the design, implementation and performance evaluation of a hardware accelerator for matrix multiplication. The accelerator is loosely coupled with the host computer via common system bus. The accelerator is composed of linear processor array (LPA), distributed memory and dedicated address generator unit. Mathematical procedure for LPA synthesis is given. The speedup of the proposed accelerator for matrix multiplication is O(n/2), where n is a number of PEs in the array, and the efficiency is 1/2. By involving hardware AGU we achieved a speedup in data transfer of approximately 2.5, compared to the software implementation of address calculation, with a hardware overhead less than 1 %.

关键词： Arrays hardware Multicore processing Logic gates Transmission line matrix methods Delay

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Reliable software for unreliable hardware: Embedded code generation aiming at reliability 11

Reliable software for unreliable hardware: Embedded code gen...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Rehman, Semeen Shafique, Muhammad Kriebel, Florian Henkel, Jörg Karlsruhe Germany

ISBN: (纸本)9781450307154

A compilation technique for reliability-aware software transformations is presented. An instruction-level reliability estimation technique quantifies the effects of hardware-level faults at the instruction-level while considering spatial and temporal vulnerabilities. It bridges the gap between hardware - where faults occur according to our fault model - and software (the abstraction level where we aim to increase reliability). For a given tolerable performance overhead, an optimization algorithm compiles an application software with respect to a tradeoff between performance and reliability. Compared to performance-optimized compilation, our method incurs 60%-80% lower application failures, averaged over various fault injection scenarios and fault rates. Copyright 2011 ACM.

关键词： Embedded systems

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A design methodology to implement memory accesses in high-level synthesis 11

A design methodology to implement memory accesses in high-le...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Pilato, Christian Ferrandi, Fabrizio Sciuto, Donatella Dipartimento di Elettronica ed Informazione Politecnico di Milano Milano 20133 Italy

ISBN: (纸本)9781450307154

Nowadays, the memory synthesis is becoming the main bottleneck for the generation of efficient hardware accelerators. This paper presents a design methodology to efficiently and automatically implement memory accesses in High-Level synthesis. In particular, the approach starts from a behavioral specification (in pure C language) and a set of design constraints, such as the memory addresses where some of the data are stored. The methodology classifies which variables can be internally or externally allocated to the different modules to generate the proper architecture, fully supporting a wide range of C constructs, such as pointer arithmetic, function calls and array accesses. Moreover it allows to parallelize the accesses when the memory address is known at compile time, resulting in an efficient execution of the specification. Copyright 2011 ACM.

关键词： High level synthesis

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