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system-level design space exploration for three-dimensional (3D) SoCs 11

System-level design space exploration for three-dimensional ...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Zou, Qiaosha Chen, Yibo Xie, Yuan Su, Alan Computer Science and Engineering Pennsylvania State University United States Synopsys Inc. Hsinchu Taiwan

ISBN: (纸本)9781450307154

Three-dimensional (3D) ICs promise to overcome barriers in integration density and interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. 3D integration provides additional architectural and technology-related design options for future system-on-chip (SoC) designs, making the early design space exploration more critical. This paper proposes a system-level design partition and hardware/ software co-synthesis framework for 3D SoC integration. The proposed methodology can be used to explore the enlarged design space and to find out the optimal design choices for given design constraints including form factor, performance, power, or yield. Copyright 2011 ACM.

关键词： system-on-chip

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system-level power and timing variability characterization to compute thermal guarantees 11

System-level power and timing variability characterization t...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Kumar, Pratyush Thiele, Lothar Computer Engineering and Networks Laboratory ETH Zurich Switzerland

ISBN: (纸本)9781450307154

With ever-increasing power densities, temperature management using software and hardware techniques has become a necessity in the design of modern electronic systems. Such techniques have to be validated and optimized with respect to the thermal guarantee they provide, i.e., a safe upperbound on the peak temperature of the system under all operating conditions. The computation of such a guarantee depends on the power and timing characteristics of the system. In this paper, we present formalisms to capture such characteristics at the system-level and provide an analytical technique to compute a provably safe upper-bound on the peak temperature. The proposed characterization and analysis is general in that it considers an impulse-responsebased thermal model, task-dependent power consumption, tasks with dynamic arrival patterns and variable resource demand, and a scheduling policy expressed as a hierarchical composition of several commonly used policies. Copyright 2011 ACM.

关键词： Timing circuits

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Branch penalty reduction on IBM cell SPUs via software branch hinting 11

Branch penalty reduction on IBM cell SPUs via software branc...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Lu, Jing Kim, Yooseong Shrivastava, Aviral Huang, Chuan Compiler Microarchitecture Lab Arizona State University Tempe AZ 85281 United States

ISBN: (纸本)9781450307154

As power-efficiency becomes paramount concern in processor design, architectures are coming up that completely do away with hardware branch prediction, and rely solely on software branch hinting. A popular example is the Synergistic Processing Unit (SPU) in the IBM Cell processor. To be able to minimize the branch penalty using branch hint instructions, in addition to estimating the branch probabilities (which has been looked at before [6, 25, 24]), it is important to carefully insert branch hints. Towards this, in this paper, we i) construct a branch penalty model for compiler, ii) formulate the problem of minimizing branch penalty using branch hinting and iii) propose a heuristic to solve this problem. The heuristic is based on three basic techniques that we introduce in this paper: NOP padding, hint pipelining, and nested loop restructuring. Experimental results on several benchmarks show that our solution can reduce the branch penalty as much as 35.4% over the previous approach. Copyright 2011 ACM.

关键词： Program compilers

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SoC-TM: Integrated HW/SW support for transactional memory programming on embedded MPSoCs 11

SoC-TM: Integrated HW/SW support for transactional memory pr...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Ferri, Cesare Bahar, Iris. Marongiu, Andrea Benini, Luca Lipton, Benjamin Moreshet, Tali Herlihy, Maurice School of Engineering Brown University Providence RI 02912 United States DEIS University of Bologna Viale Risorgimento 2 40136 Bologna Italy Engineering Dept Swarthmore College Swarthmore PA 19081 United States Computer Science Dept Brown University Providence RI 02912 United States

ISBN: (纸本)9781450307154

Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP- SoCs. Our proposal leverages a hardware Transactional Memory (HTM) design, based on a dedicated HW module for conflict management, whose functionality is exposed to the software through compiler directives, implemented as an extension to the popular OpenMP programming model. To further improve ease of programming, our framework sup- ports speculative parallelism, thanks to the ability of enforcing a given commit order in hardware. Our experimental results confirm that SoC-TM is a viable and cost-effective solution for embedded MPSoCs, in terms of energy, performance and productivity. Copyright 2011 ACM.

关键词： system-on-chip

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Dominator homomorphism based code matching for source-level simulation of embedded software 11

Dominator homomorphism based code matching for source-level ...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Stattelmann, Stefan Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 D-76131 Karlsruhe Germany University of Tuebingen Sand 13 D-72076 Tuebingen Germany

ISBN: (纸本)9781450307154

Relating optimized binary code and the source-level statements from which it was created can be challenging if an optimizing compiler was used to create the machine code. Moreover, this relation is crucial if a compiler-optimized program must be debugged or results from a low-level analysis need to be mapped to the source code to perform manual optimizations. Existing approaches for the debugging of optimized code usually require pervasive changes in the compiler and hence are not available for all architectures. Methods for analyzing non-functional properties of software components in complex systems (i.e. execution time and power consumption) often have similar constraints, if compiler optimizations are supported at all. This paper proposes two novel concepts to overcome these issues. To precisely relate source-level statements with the respective compiler-generated machine code, a method to reconstruct and disambiguate debug information is presented. Based on this information, an instrumentation technique is introduced which allows accurately simulating the execution of optimized binary code at the source code level. Experimental results show that by using this technique, arbitrary low-level properties of software components can be evaluated in a fast and accurate manner without running the software on the actual target hardware. Copyright 2011 ACM.

关键词： Binary codes

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Constraint-driven synthesis and tool-support for flexray-based automotive control systems 11

Constraint-driven synthesis and tool-support for flexray-bas...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Schneider, Reinhard Goswami, Dip Zafar, Sohaib Chakraborty, Samarjit Lukasiewycz, Martin TU Munich Germany TUM CREATE Singapore

ISBN: (纸本)9781450307154

Emerging bus protocols such as FlexRay provide an expedient platform for the design of automotive control systems due to its high bandwidth and deterministic temporal behavior. However, the choice of suitable platform parameters such as task and message schedules becomes a challenging design problem as the protocol is complex in nature and enforces a tight coupling between local task schedules on ECUs and global bus schedules. Although there exist several commercial off-the-shelf (COTS) design tools for FlexRay and control systems, current tools do not provide any mechanism for automatically synthesizing the platform parameters from the controller specifications. In this work we synthesize controllers subject to specified control goals while taking into account platform-specific properties. In particular, we translate the timing constraints derived from the control design into platform constraints that need to be satisfied by the control-related tasks and messages. For this purpose, we formulate and solve a constraint satisfaction problem (CSP) to synthesize feasible platform parameters that can be realized by the underlying operating systems and the FlexRay bus. Our design flow may be easily integrated with existing FlexRay design tools and will significantly ease (and automate) the existing design process. We show the applicability of our results by implementing two automotive control systems on a hardware-in-the-Loop (HiL) setup and study how different bus configurations affect the controller synthesis and the choice of platform parameters. Copyright 2011 ACM.

关键词： Cyber Physical system

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Rigorous system level modeling and analysis of mixed HW/SW systems 11

Rigorous system level modeling and analysis of mixed HW/SW s...

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proceedings of the Ninth ACM/IEEE international conference on Formal Methods and Models for codesign

作者： Bourgos, P. Basu, A. Bozga, M. Bensalem, S. Sifakis, J. Huang, K. UJF-Grenoble 1 / CNRS VERIMAG UMR 5104 Grenoble F-38041 France Institute of VLSI Design Zhejiang University China

ISBN: (纸本)9781457701160

A grand challenge in complex embedded systems design is developing methods and tools for modeling and analyzing the behavior of an application software running on multicore or distributed platforms. We propose a rigorous method and a tool chain that allows to obtain a faithful model representing the behavior of a mixed hardware/software system from a model of its application software and a model of its underlying hardware architecture. The system model can be simulated and analyzed for validation of both functional and extra-functional properties. The tool chain uses DOL (Distributed Operation Layer [1]) as the frontend for specifying the application software and hardware architecture, and BIP (Behavior Interaction Priority [2]) as the modeling and analysis framework. It is illustrated through the construction of system models of MJPEG and MPEG2 decoder applications running on MPARM, a multicore architecture. © 2011 IEEE.

关键词： Application programs

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hardware/software Co-design for Fast-trainable Speaker Identification system Based on SMO

Hardware/Software Co-design for Fast-trainable Speaker Ident...

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IEEE international conference on systems, Man and Cybernetics (SMC)

作者： Wang, Jhing-Fa Peng, Jr-Shiang Wang, Jia-Ching Lin, Po-Chuan Kuan, Ta-Wen Natl Cheng Kung Univ Dept Elect Engn 1 Univ Rd Tainan 70101 Taiwan Natl Cent Univ Dept Comp Sci & Informat Engn Jhongli Taiwan Tung Fang Deign Univ Dept Elect Engn & Comp Sci Kaohsiung Taiwan

ISBN: (纸本)9781457706530

Embedded speaker identification system is a popular research, but most of current systems can not provide fast training ability. Because of the low computational ability in the embedded environment, a large amount of waiting time usually makes the human-machine interface not friendly. This paper presents a hardware and software (HW/SW) co-design solution for fast-trainable speaker identification system. Fast training ability makes this embedded speaker identification system possess high flexibility and enhances the convenience to a wide range of real-world applications. The proposed system consists of a training phase and a multiclass identification phase. The sequential minimal optimization (SMO) training algorithm occupies the heaviest computational load and is realized as a dedicated VLSI module, i.e., the hardware component. The other processes such as speech preprocess, speech feature extraction, and SVM voting strategy are implemented by software. Moreover, a data-packed mechanism is presented to improve the bandwidth utilization. Compared with the embedded C code based on ARM processor, our system reduces 90% of the training time and achieves 89.9% identification rate with the NIST 2010 speaker recognition database. The proposed system was tested and found to be fully functional working on a Socle CDK prototype system with an AMBA based Xilinx FPGA and an ARM926EJ processor.

关键词： Speaker Identification hardware/software codesign Sequential Minimal Optimization (SMO)

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Managing large HW/SW codesign projects

Managing large HW/SW Codesign projects

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6th IEEE international conference on Intelligent Data Acquisition and Advanced Computing systems: Technology and Applications, IDAACS'2011

作者： Wolff, Carsten Gorrochategui, Idania Bücker, Markus University of Applied Sciences and Arts Dortmund Emil-Figge-Str. 42 44227 Dortmund Germany University of the Basque Country - Bilbao Barrio Sarriena S/n 48940 Leioa Bizkaia Spain Intel Mobile Communcations GmbH Düsseldorfer Landstr. 401 47259 Duisburg Germany

ISBN: (纸本)9781457714238

HW/SW codesign [4] is a strategy to develop highly optimized systems composed of both electronics hardware and software. Examples are smartphones, consumer electronics or embedded systems. The challenge is to achieve an optimized split by partitioning the system components into hardware and software and to achieve the best project execution time (and cost) by developing both hardware and software concurrently [1]. If such systems contain hundreds of highly interdependent hardware and software components, the R&D project for such a system becomes large and very complex. Since more HW/SW systems are developed and since the complexity is growing, a specialized project management methodology for this kind of projects is emerging. Our contribution is focused on giving a practical overview of the challenges and best practices for the management of such projects. The findings are based on more than 10 years industrial experience with various large smartphone and consumer electronics projects. Currently, these findings are evaluated in a research project. This contribution gives an overview on the scope and future targets of this project. © 2011 IEEE.

关键词： Smartphones

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A single processor approach for loosely synchronized execution of parallel flows on heterogeneous multicore

A single processor approach for loosely synchronized executi...

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international conference on Computational Science (ICCS) on the Ascent of Computational Excellence

作者： Louise, Stephane David, Vincent Calcado, Fabien LIST CEA F-91191 Gif Sur Yvette France

Multicore is quickly becoming the norm, even in the embedded world. This trend is thought to be sustained as long as the progress of micro-electronics will permit, by regularly doubling the number of available computing cores on a given chip. That means that multicore aware programs are no longer an option, but at the same time, parallel programming is still very hard nowadays despite progresses in parallel languages. From these observations, we investigated how to use multicore in a fashion that would be as close as possible as single processor programming, at least from the program design and debug point of view, by a kind of generalization of the superscalar design. One of the aim is also to guarantee little latency and synchronization overheads: for that a loose synchronization mechanism called "weak synchronization" is described. It is supported by a hardware/OS co-design. Some first evaluations of the system performance are provided.

关键词： Multicore processor execution model hardware/software codesign OS for parallel execution

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