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A single processor approach for loosely synchronized execution of parallel flows on heterogeneous multicore

A single processor approach for loosely synchronized executi...

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international conference on Computational Science (ICCS) on the Ascent of Computational Excellence

作者： Louise, Stephane David, Vincent Calcado, Fabien LIST CEA F-91191 Gif Sur Yvette France

Multicore is quickly becoming the norm, even in the embedded world. This trend is thought to be sustained as long as the progress of micro-electronics will permit, by regularly doubling the number of available computing cores on a given chip. That means that multicore aware programs are no longer an option, but at the same time, parallel programming is still very hard nowadays despite progresses in parallel languages. From these observations, we investigated how to use multicore in a fashion that would be as close as possible as single processor programming, at least from the program design and debug point of view, by a kind of generalization of the superscalar design. One of the aim is also to guarantee little latency and synchronization overheads: for that a loose synchronization mechanism called "weak synchronization" is described. It is supported by a hardware/OS co-design. Some first evaluations of the system performance are provided.

关键词： Multicore processor execution model hardware/software codesign OS for parallel execution

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IOPT Petri Net State Space Generation Algorithm with Maximal-Step Execution Semantics

IOPT Petri Net State Space Generation Algorithm with Maximal...

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9th IEEE international conference on Industrial Informatics (INDIN)

作者： Pereira, Fernando Moutinho, Filipe Gomes, Luis Campos-Rebelo, Rogerio ISEL Inst Super Engenharie Lisboa Lisbon Portugal Univ Nova Lisboa CTS Caparica Portugal

ISBN: (纸本)9781457704345

This paper presents an algorithm to efficiently generate the state-space of systems specified using the IOPT Petri-net modeling formalism. IOPT nets are a non-autonomous Petri-net class, based on Place-Transition nets with an extended set of features designed to allow the rapid prototyping and synthesis of system controllers through an existing hardware-software co-design framework. To obtain coherent and deterministic operation, IOPT nets use a maximal-step execution semantics where, in a single execution step, all enabled transitions will fire simultaneously. This fact increases the resulting state-space complexity and can cause an arc "explosion" effect. Real-world applications, with several million states, will reach a higher order of magnitude number of arcs, leading to the need for high performance state-space generator algorithms. The proposed algorithm applies a compilation approach to read a PNML file containing one IOPT model and automatically generate an optimized C program to calculate the corresponding state-space.

关键词： Algorithm design and analysis C language C program Fires Firing Generators IOPT Petri net generation algorithm IOPT Petri-net modeling formalism PNML file Petri nets Semantics software system recovery arc explosion effect compilation approach computational complexity formal verification hardware-software codesign framework input-output place-transition Petri nets maximal-step execution semantics model checking approach place-transition nets program compilers rapid prototyping state-space complexity

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An FPGA-based implementation of HW/SW architecture for CFAR radar target detector

An FPGA-based implementation of HW/SW architecture for CFAR ...

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2011 23rd international conference on Microelectronics, ICM 2011

作者： Djemal, Ridha Belwafi, Kais Kaaniche, Walid Alshebeili, Saleh A. Electrical Engineering Department College of Engineering King Saud University Box 800 11421 Saudi Arabia ENISO Avenue 18 Janvier 1952 Sousse Tunisia

ISBN: (纸本)9781457722073

This paper presents an efficient HW/SW codesign FPGA-based architecture of B-ACOSD CFAR target detector in log normal distribution for radar system. All CFAR system modules are analyzed in order to identify the critical ones to be optimized so that the detection process will be conducted in realtime. To compel the design optimization of CFAR Architecture, we have considered the custom instruction approach offered by Altera environment. Furthermore HW/SW architecture of the CFAR detector is carried out where the NIOS II execute the software part and communicate via the Avalon switch fabric with the hardware modules represented by the custom logic components, on-chip memories, UART and JTAG interfaces. The proposed system-on-chip is validated and tested using the Stratix IV EP4SGX230KF4C2 of Altera operating at 250MHz. Using the HW/SW approach for our embedded target detection system, we improved the performance of the architecture compared to the pure software one with a total delay of 0.45 μs. © 2011 IEEE.

关键词： system-on-chip

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CODES+ISSS keynote: To alert, rescue and recover: Critical information technologies for managing mega disasters

CODES+ISSS keynote: To alert, rescue and recover: Critical i...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jane W. S. Liu Institute of Information Science and Research Center for Information Technology Innovations Academia Sinica Taiwan

This talk will discuss why despite recent advances, state-of-the-art disaster management IT infrastructures and information systems are not as effective as they should be for managing mega calamitous events of unforeseen sizes and severity. It will then discuss critical gaps in information technology. Examples include methodologies, tools and middleware for: ▪ Exploitation of complementary network technologies to prevent communication failures during disasters; ▪ Flexible and responsive management of logical connectivity and information flow among information sources, fusion modules, applications and end-users, providing them with support for pub/sub messaging, syndication and feed services, dynamic event-triggered messaging and so on; ▪ Trustworthy information brokerage services for safe and responsive emergency access and flow control of information from independently developed information sources owned by government agencies, businesses, institutions, NGOs, communities, private property owners and individuals; ▪ Common models and views, open standard interfaces and API functions to enable independent development of disaster management applications and services; ▪ Advanced disaster management applications and services.

关键词： Information technology Information science Disaster management Real time systems Awards activities software Information systems

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Session details: Tools and algorithms for exploration and synthesis of distributed embedded systems 11

Session details: Tools and algorithms for exploration and sy...

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proceedings of the seventh IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Hiroyuki Tomiyama Todor Stefanov Ritsumeikan University Leiden University

No abstract available.

ISBN: (纸本)9781450307154

No abstract available.

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Design of a Novel Digital Phantom for EIT system Calibration

Design of a Novel Digital Phantom for EIT System Calibration

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33rd Annual international conference of the IEEE Engineering-in-Medicine-and-Biology-Society (EMBS)

作者： Li, Nan Wang, Wei Xu, Hui Natl Univ Def Technol Sch Elect Sci & Engn Changsha 410073 Hunan Peoples R China Univ Sussex Biomed Engn Res Grp Brighton BN1 9QT E Sussex England Univ Sussex Brighton BN1 9QT E Sussex England Natl Univ Def Technol Changsha 410073 Peoples R China

ISBN: (纸本)9781424441228

This paper presented the design method of a novel digital phantom for electrical impedance tomography system calibration. By current sensing, voltage generating circuitry and digital processing algorithms implemented in FPGA, the digital phantom can simulate different impedances of tissues. The hardware of the digital phantom mainly consists of current sensing section, voltage generating section, electrodes switching section and a FPGA. Concerning software, the CORDIC algorithm is implemented in the FPGA to realize direct digital synthesis (DDS) technique and related algorithms. Simulation results show that the suggested system exhibits sufficient accuracy in the frequency range 10 Hz to 2 MHz. With the advantages offered by digital techniques, our approach has the potential of speed, accuracy and flexibility of the EIT system calibration process.

关键词： CORDIC algorithm Calibration DDS technique EIT system calibration Electrodes FPGA Field programmable gate arrays Impedance Phantoms Sensors Tomography bioelectric phenomena biological tissues biotissue impedance current sensing digital phantom design digi

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system-level design exploration for 3-D stacked memory architectures 11

System-level design exploration for 3-D stacked memory archi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chi-Hung Lin Wen-Tsan Hsieh Hsien-Ching Hsieh Chun-Nan Liu Jen-Chieh Yeh Information and Communications Research Laboratories Industrial Technology Research Institute Hsinchu Taiwan

ISBN: (纸本)9781450307154

Summary form only given. Traditional technology scaling of semiconductor chips followed Moore's Law. However, the transistor performance improvement will be limited, and designer will not see doubling of frequency every two years. Recently, three-dimension integrated circuits (3D IC) that employ the vertically through-silicon vias (TSVs) for connecting each of dies have been proposed. It is an alternative solution to existent Package-on-Package (PoP) and system-in-Package (SiP) processes. There are many benefits by using TSV-based 3-D integration technologies: (1) more functionality can be integrated into a small silicon space for form factor reduction, (2) circuit delay can be improved by using TSVs due to the shorter interconnect and reduced parasitic capacitance/inductance, (3) different components with incompatible manufacturing process (i.e. Logic, DRAM, Flash, etc) can be combined in single 3-D IC for heterogeneous integration. In addition, there are many 3-D multi-core or many-core architectures are discussed recently. Comparing with traditional two-dimension multi-core or many-core architectures, the major difference is memory bandwidth problem can be addressed by stacked memory architecture. Intel has good demonstration through the teraflops microprocessor chip which is an 80-core design with memory-on-logic architecture. And, each core connects to a 256KB SRAM with 12GB/s bandwidth. Although 3-D stacking technology can bring us many benefits for next generation integrated circuits, it comes with many problems and challenges in system-level design. For instance, 3-D IC designs will deal with serious challenges in design space exploration and system validation. For most designs, the number of TSV will be the most critical limitation that should be considered carefully. Besides, system design by 3-D IC will become more and more complex, and it needs a full system-level solution to face the performance, number of TSV, and power issues of 3D-IC. Furthermore, it

关键词： Through-silicon vias Integrated circuit modeling Stacking Multicore processing Random access memory

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Design and realization of CAN bus vehicle instrument cluster based on μ C/OS-II

Design and realization of CAN bus vehicle instrument cluster...

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2011 2nd international conference on Mechanic Automation and Control Engineering, MACE 2011

作者： Dai, Jiejie Song, Hui New Main Building D645 of Beihang University Beijing China School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9781424494392

A kind of CAN bus vehicle instrument cluster is studied and designed in this paper based on the CAN (Controller Area Network)bus technology. This vehicle instrument cluster uses MC9S12XHZ512 dual-core processor as the main controller, containing signal input module, data processing module and display module which compose the hardware platform. The software adopts the high reliability real-time kernel μ C/OS-II embedded operating system to accomplish the system's functions with modular and hierarchical *** system design adds vehicle instrument cluster to the body network and reflects the real vehicle condition by receiving,processing and displaying the data through CAN bus and vehicle sensors. This system greatly reduces design circuit and cost. © 2011 IEEE.

关键词： Control system synthesis

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Managing large HW/SW codesign projects

Managing large HW/SW Codesign projects

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IEEE international Workshop on Intelligent Data Acquisition and Advanced Computing systems: Technology and Applications

作者： Carsten Wolff Idania Gorrochategui Markus Bücker University of Applied Sciences and Arts Dortmund Dortmund Germany University of the Basque Country Bilbao Leioa Bizkaia Spain Intel Mobile Communications GmbH Duisburg Germany

HW/SW codesign [4] is a strategy to develop highly optimized systems composed of both electronics hardware and software. Examples are smartphones, consumer electronics or embedded systems. The challenge is to achieve an optimized split by partitioning the system components into hardware and software and to achieve the best project execution time (and cost) by developing both hardware and software concurrently [1]. If such systems contain hundreds of highly interdependent hardware and software components, the R&D project for such a system becomes large and very complex. Since more HW/SW systems are developed and since the complexity is growing, a specialized project management methodology for this kind of projects is emerging. Our contribution is focused on giving a practical overview of the challenges and best practices for the management of such projects. The findings are based on more than 10 years industrial experience with various large smartphone and consumer electronics projects. Currently, these findings are evaluated in a research project. This contribution gives an overview on the scope and future targets of this project.

关键词： software hardware Synchronization Project management Prototypes Planning Delay

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A novel approach for system level synthesis of multi-core system architectures from TPG models

A novel approach for system level synthesis of multi-core sy...

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9th ACS/IEEE international conference on Computer systems and Applications, AICCSA 2011

作者： Yehia, Karim Safar, Mona Youness, Hassan AbdElSalam, Mohamed Salem, Ashraf Department of Electronics and Communications Engineering Cairo University Cairo Egypt Department of Computers and Systems Engineering Ain-Shams University Cairo Egypt Mentor Graphics Egypt Cairo Egypt

ISBN: (纸本)9781457704741

A multi-processor system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a novel approach to synthesize multi-core system architectures from Task Precedence Graphs (TPG) models. The front end engine applies efficient algorithm for scheduling and communication contention resolving to obtain the optimal multi-core system architecture in terms of number of processor cores, number of busses, task-to-processor/channel-to-bus mapping, optimal schedule, and hardware-software (HW-SW) partition. The scheduling and mapping algorithms produce the optimality of mapping tasks onto cores. The partitioning technique reduces the overall execution time and number of buses among the cores. The back end engine generates a systemC simulation model using a well-known commercial tool model generation library. The viability and potential of the proposed algorithms are demonstrated by a case study and extensive experimental results to conclude that the proposed approach is an efficient scheme to obtain the optimality of scheduling, mapping and partitioning with hard and large task graph problems. © 2011 IEEE.

关键词： Scheduling

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