The proceedings contain 46 papers. The topics discussed include: concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design;a time-predictable system initialization design...
ISBN:
(纸本)9781605584706
The proceedings contain 46 papers. The topics discussed include: concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design;a time-predictable system initialization design for huge-capacity flash-memory storage systems;deterministic service guarantees for NAND flash using partial block cleaning;static analysis of processor stall cycle aggregation;application specific non-volatile primary memory for embedded systems;scratchpad allocation for concurrent embedded software;hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits;a performance-oriented hardware/software partitioning for datapath applications;traversal caches: a first step towards FPGA acceleration of pointer-based data structures;and distributed and low-power synchronization architecture for embedded multiprocessors.
The proceedings contain 120 papers. The special focus in this conference is on Computer Aided systems Theory. The topics include: Solving a real–world FAP using the scatter search metaheuristic;on the success rate of...
ISBN:
(纸本)9783642047718
The proceedings contain 120 papers. The special focus in this conference is on Computer Aided systems Theory. The topics include: Solving a real–world FAP using the scatter search metaheuristic;on the success rate of crossover operators for genetic programming with offspring selection;on structural identification of 2d regression functions for indoor bluetooth localization;grid-enabled mutation-based genetic algorithm to optimise nuclear fusion devices;priority rule generation with a genetic algorithm to minimize sequence dependent setup costs;a grasp–vns hybrid for the fuzzy vehicle routing problem with time windows;performance modelling for avionics systems;object-oriented petri nets-based modeling of resources in project engineering;simulation based design of control systems using devs and petri nets;learning autonomous helicopter flight with evolutionary reinforcement learning;Transforming UML-based system descriptions into simulation models as part of system development frameworks;model-based design and verification of reactive systems;resonant tunnelling diode-based circuits: Simulation and synthesis;a practical methodology for integration testing;safety oriented laparoscopic surgery training system;Co-operative extended kohonen mapping (EKM) for wireless sensor networks;morphotronic system applications;sniper: A wireless sensor network simulator;embedded fortress –software environment for intellectual property protection in embedded systems;collaborative xml document versioning;designing communication space in wireless sensor network based on relational attempt;parallel distributed genetic algorithm for expensive multi-objective optimization problems;boundary scan security enhancements for a cryptographic hardware;automated design of totally self-checking sequential circuits;a general purpouse control system;on the first exit time problem for a gompertz-type tumor growth;diffusion processes subject to catastrophes;preface.
In order to resolve a problem of how to real-time monitor mine water inflow, the novel synthesis conversion method is brought forward, it describe relation of water level and flux. A real-time monitoring system for mi...
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Real world applications constitute intellectual property and simultaneous design of hardware and software is made very difficult due to the need for disclosing proprietary software to hardware designers. Consider a sm...
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ISBN:
(纸本)9781450305198
Real world applications constitute intellectual property and simultaneous design of hardware and software is made very difficult due to the need for disclosing proprietary software to hardware designers. Consider a smart phone for which applications are developed by various third parties or a military system, where the classified applications are developed in-house at the military while hardware is procured from standard vendors. Design of hardware that gives good performance and low power can be done if hardware designers had access to the software, so they can understand the features of the software and tune various hardware features to the software characteristics. While non-disclosure agreements and legal arrangements can be used to partly solve the problem, it will be much more convenient to have a mechanism to create proxies of proprietary benchmarks that have the performance (and power) characteristics of the source, but not the *** our past research, we created a benchmark synthesis process for early design exploration. The benchmark synthesis process consists of constructing a proxy workload that possesses approximately the same performance and power characteristics as the original workload [1-3]. The synthesis comprises of two steps: (1) profiling the real-world proprietary workload to measure its inherent behavior characteristics, and (2) modeling the measured workload attributes into a synthetic benchmark program. The set of workload characteristics can be thought of as a signature that uniquely describes the workload's inherent behavior, independent of the microarchitecture. The cloned code in fact has no functionality and cannot be reverse engineered to create the original code or algorithms. The cloned software can be freely released to hardware developers so that they can optimize the hardware they deliver to their clients to yield improved *** talk will describe the benchmark synthesis process as well as the status of the r
This special session aims to introduce to the hardware/softwarecodesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system desig...
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ISBN:
(纸本)9781605589053
This special session aims to introduce to the hardware/softwarecodesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system design have traditionally been considered as two separate areas of research, they in fact share quite some common features, especially as CMOS devices continue along their scaling trends and the HPC community hits hard power and energy limits. Understanding the similarities and differences between the design practices adopted in the two areas will help bridge the two communities and lead to design tool developments benefiting both communities.
Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel ...
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ISBN:
(纸本)9781605589053
Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel simulation approach along with a systemC framework to accelerate tightly-coupled MPSoC simulations on multi-core hosts. Key contribution is the implementation strategy, which utilizes techniques from the high-performance computing domain. Results show speed-ups of up to 4.4 on four host cores.
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safety-critical applications. An applicati...
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ISBN:
(纸本)9781605589053
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.
In this paper we propose a synthesis semantics for systemC™ channels, which contribute to a clear separation between computation (algorithm) and communication, whereas communication related parts are modelled through ...
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ISBN:
(纸本)9781605589053
In this paper we propose a synthesis semantics for systemC™ channels, which contribute to a clear separation between computation (algorithm) and communication, whereas communication related parts are modelled through either primitive or hierarchical channels. We present a synthesisable replacement for systemC primitive channels that allows deterministic access scheduling and user-constrained refinement for HW/HW and HW/SW communication. We demonstrate the feasibility of our approach through synthesis and exploration of a communication intensive packet switch design under consideration of different configurations and communication refinements.
Real-time decoding of ultrahigh resolution video using multicore architectures is important for future embedded systems. However, memory bandwidth is still a bottleneck of system performance. Video coding performs irr...
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ISBN:
(纸本)9781605589053
Real-time decoding of ultrahigh resolution video using multicore architectures is important for future embedded systems. However, memory bandwidth is still a bottleneck of system performance. Video coding performs irregular DRAM access resulting in very low and unstable efficiency. The conventional cache approach is insufficient because it reduces only the redundant accesses to data that has already been fetched during prior-macroblock decoding. We present an Elastic software Cache (ESC) for ultrahigh resolution video decoding on Scratchpad Memory (SPM)-based systems. Utilizing access region analysis, our latency-optimized prefetching scheme rearranges accesses to minimize both data redundancy and DRAM access latency. Compared to the conventional cache approach, our scheme requires only 4.6 Kbytes of SPM space but it can save up to 25% of memory access cycles resulting in both higher performance and lower power.
Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottleneck in platform-based design. As a reme...
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ISBN:
(纸本)9781605589053
Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottleneck in platform-based design. As a remedy, the work at hand proposes a novel automatic platform-based systemsynthesis procedure, inspired by techniques developed in the context of automatic system verification known as Satisfiability Modulo Theories. It tightly couples the computation of a feasible allocation and binding with nonfunctional constraint checking where, in contrast to existing approaches, not only linear constraints but even nonlinear constraints are supported. This allows to efficiently prove whether there exists a feasible implementation of a set of applications on the given platform with respect to both, functional and nonfunctional constraints. Moreover, an approach for early learning based on feasibility checking of partial implementations is proposed that can signifiantly improve the synthesis runtime, especially in case the selected platform imposes stringent constraints on the implementation. The effectiveness of this approach is shown for an automotive ECU network design that requires Modular Performance Analysis to ensure non-functional nonlinear timing constraints.
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