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Improving platform-based system synthesis by satisfiability Modulo theories solving 10

Improving platform-based system synthesis by satisfiability ...

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Reimann, Felix Glab, Michael Haubelt, Christian Eberl, Michael Teich, Jürgen University of Erlangen Nuremberg Germany

ISBN: (纸本)9781605589053

Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottleneck in platform-based design. As a remedy, the work at hand proposes a novel automatic platform-based system synthesis procedure, inspired by techniques developed in the context of automatic system verification known as Satisfiability Modulo Theories. It tightly couples the computation of a feasible allocation and binding with nonfunctional constraint checking where, in contrast to existing approaches, not only linear constraints but even nonlinear constraints are supported. This allows to efficiently prove whether there exists a feasible implementation of a set of applications on the given platform with respect to both, functional and nonfunctional constraints. Moreover, an approach for early learning based on feasibility checking of partial implementations is proposed that can signifiantly improve the synthesis runtime, especially in case the selected platform imposes stringent constraints on the implementation. The effectiveness of this approach is shown for an automotive ECU network design that requires Modular Performance Analysis to ensure non-functional nonlinear timing constraints.

关键词： Formal logic

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Towards formal system-level verification of security requirements during hardware/software codesign

Towards formal system-level verification of security require...

引用

IEEE international SOC conference

作者： Loinig, Johannes Steger, Christian Weiss, Reinhold Haselsteiner, Ernst Institute for Technical Informatics Graz University of Technology Graz Austria NXP Semiconductors Austria GmbH Gratkorn Austria

ISBN: (纸本)9781424466832

Today's embedded systems have to fulfill sophisticated security requirements. They have a deep impact into the system's design. Security can only be achieved if security requirements are considered during the system-wide design and development process. In this concept work1 we propose a hardware/software codesign approach that addresses functional security requirements during all design and development phases of a system. © 2010 IEEE.

关键词： hardware-software codesign

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Statistical approach in a system level methodology to deal with process variation 10

Statistical approach in a system level methodology to deal w...

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Sanz Pineda, Concepción Prieto, Manuel Gómez, José Ignacio Tenllado, Christian Catthoor, Francky Dpto. de Arquitectura de Computadores Y Automática Universidad Complutense de Madrid Madrid 28040 Spain Inter-University Microelectronics Center IMEC Leuven 3001 Belgium

ISBN: (纸本)9781605589053

The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of both energy consumption and performance. In this context, developing variation aware design methodologies becomes a must. These techniques should provide better performance-energy balances while the percentage of faulty products keeps controlled. Furthermore, it would be advisable to consider adaptations of the system during lifetime, in order to provide robustness against ageing. In this paper we propose a design approach which tackles process variation on the memory system by using multimode memories. At design time we perform a heuristic exploration using probabilistic models of these memories, which generates a set of system configurations that minimize energy consumption for a given set of timing constraints. The percentage of systems that will satisfy these deadlines, even under process variation, is taken as a design parameter. Additionally, if system monitors are available, a setup stage optimizes the initial set of configurations for the actual memory parameters. Our simulations show that this methodology provides significant energy savings while still meeting timing constraints. © 2010 ACM.

关键词： Energy utilization

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FEMU: A firmware-based emulation framework for SoC verification 10

FEMU: A firmware-based emulation framework for SoC verificat...

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Li, Hao Tong, Dong Huang, Kan Cheng, Xu Microprocessor Research and Development Center Peking University Beijing China

ISBN: (纸本)9781605589053

Full-system emulation on FPGA(Field-Programmable Gate Array) with real-world workloads can enhance the confidence of SoC(system-on-Chip) design. However, since FPGA emulation requires complete implementation of key modules and provides weak visibility, it is time-consuming. This paper proposes FEMU, a hybrid firmware/hardware emulation framework for SoC verification. The core of FEMU is implemented by transplanting QEMU, a full-system emulator, from OS level to BIOS level, so we can directly emulate devices upon hardware. Moreover, FEMU provides programming interfaces to simplify device modeling in firmware. Based on an auxiliary set of hardware modules, FEMU allows hybrid full-system emulation with the combination of real hardware and emulated firmware model. Therefore, FEMU can facilitate full-system emulation in three aspects. First, FEMU enables full-system emulation with the minimum hardware implementation, so the DUT (Design Under Test) module can be verified under target application as early as possible. Second, by comparing the execution traces generated using real hardware and emulated firmware model, respectively, FEMU helps locate and fix bugs occurred in the full-system emulation. Third, by replacing un-verified hardware modules with emulated firmware models, FEMU helps isolating design issues in multiple modules. In a practical SoC project, FEMU helped us identify several design issues in full-system emulation. In addition, the evaluation results show that the emulation speed of FEMU is comparable with QEMU after transplantation.

关键词： system-on-chip

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Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming 10

Automatic parallelization of embedded software using hierarc...

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Cordes, Daniel Marwedel, Peter Mallik, Arindam Informatik Centrum Dortmund Joseph-von-Fraunhofer-Str. 20 Dortmund Germany Imec Belgium Kapeldreef 75 Leuven Belgium

ISBN: (纸本)9781605589053

The last years have shown that there is no way to disregard the advantages provided by multiprocessor system-on-Chip (MPSoC) architectures in the embedded systems domain. Using multiple cores in a single system enables to close the gap between energy consumption, problems concerning heat dissipation, and computational power. Nevertheless, these benefits do not come for free. New challenges arise, if existing applications have to be ported to these multiprocessor platforms. One of the most ambitious tasks is to extract efficient parallelism from these existing sequential applications. Hence, many parallelization tools have been developed, most of them are extracting as much parallelism as possible, which is in general not the best choice for embedded systems with their limitations in hardware and software support. In contrast to previous approaches, we present a new automatic parallelization tool, tailored to the particular requirements of the resource constrained embedded systems. Therefore, this paper presents an algorithm which automatically steers the granularity of the generated tasks, with respect to architectural requirements and the overall execution time reduction. For this purpose, we exploit hierarchical task graphs to simplify a new integer linear programming based approach in order to split up sequential programs in an efficient way. Results on real-life benchmarks have shown that the presented approach is able to speed sequential applications up by a factor of up to 3.7 on a four core MPSoC architecture.

关键词： Embedded systems

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A holistic approach to network-on-chip synthesis 10

A holistic approach to network-on-chip synthesis

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Leary, Glenn Chatha, Karam S. Department of CSE Arizona State University P.O. Box 875406 Tempe AZ 85287-5406 United States

ISBN: (纸本)9781605589053

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor system-on-Chip architectures. synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

关键词： Network-on-chip

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system-level reliability modeling for MPSoCs 10

System-level reliability modeling for MPSoCs

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Xiang, Yun Chantem, Thidapat Dick, Robert P. Hu, X. Sharon Shang, Li EECS Department University of Michigan Ann Arbor MI 48109 United States CSE Department University of Notre Dame Notre Dame IN 46556 United States ECE Department University of Colorado Boulder CO 80309 United States

ISBN: (纸本)9781605589053

The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Accurate and fast reliability modeling is a primary challenge in the design and optimization of reliable MPSoCs. This paper presents a reliability modeling framework that integrates device-, component-, and system-level models. This framework contains modules for electromigration, time-dependent dielectric breakdown, stress migration, and variable-amplitude thermal cycling. A new statistical reliability distribution is proposed for accurate characterization of components containing too few devices for an extreme value distribution to be appropriate. A hierarchical system-level survival lattice based Monte Carlo technique is used to estimate the temporal fault distributions of MPSoCs that use arbitrary static and dynamic reliability-enhancing redundancy schemes. Physical process variation, which may have a significant impact on MPSoC reliability, is considered in the model. The proposed modeling technique has 5% average error in mean time to failure and reduces simulation time by nearly 3 orders of magnitude relative to a non-hierarchical Monte Carlo technique.

关键词： Hierarchical systems

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RTOS-Aware Modeling of Embedded hardware/software systems

RTOS-Aware Modeling of Embedded Hardware/Software Systems

引用

IEEE international conference on Computer Design

作者： Mueller, Matthias Gerlach, Joachim Rosenstiel, Wolfgang Univ Tubingen Wilhelm Schickard Inst Comp Sci Dept Comp Engn D-72074 Tubingen Germany

ISBN: (纸本)9781424489350

Modern embedded systems such as mobile phones or electronic control units from the automotive domain include a bulk of highly complex and highly interacting functions. Due to several reasons-flexibility and cost effectiveness may be the most important ones-a large and permanently growing part of these functions is implemented in software. This comes along with the demand for more and more processing power, paving the way for multi-core architectures, and widespread use of real-time operating systems. Application software implementation and operating system configuration strongly influence the overall system behavior. Design methodologies for such complex systems, consisting of hardware, software and real-time operating systems, must provide an early, model-based view on the overall system. The approach described in this paper enables automatic generation of system-level models of complex systems from abstract application specifications. Additionally, a compiler-based technique allows automatic calculation of precise software runtime information and annotation of the generated model. The resulting system-level model facilitates early exploration of systems on high level of abstraction, taking into account functional and temporal characteristics of hardware, software and real-time operating system. A key feature of the approach is its high accuracy, which is shown by applying it to an industrial application from the automotive domain.

关键词： RTOS-aware modeling compiler-based technique embedded hardware-software system embedded systems hardware-software codesign operating systems (computers) program compilers system-level model

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Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications 10

Optimal synthesis of latency and throughput constrained pipe...

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Javaid, Haris He, Xin Ignjatovic, Aleksander Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781605589053

A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specific Instruction set Processors (ASIPs), called a pipelined MPSoC. The latency and throughput requirements of streaming applications put constraints on the design of such a pipelined MPSoC, where each ASIP has a number of available configurations differing by additional instructions, and instruction and data cache sizes. Thus, the design space of a pipelined MPSoC is all the possible combinations of ASIP configurations (design points). In this paper, a methodology is proposed to optimize the area of a pipelined MPSoC under a latency or a throughput constraint. The final design point is a set of ASIP configurations with one configuration for each ASIP. We proposed an Integer Linear Programming (ILP) based solution to the area optimization problem under a latency constraint, and an algorithm for optimization of pipelined MPSoC area under a throughput constraint. The proposed solutions were evaluated using four streaming applications: JPEG encoder;JPEG decoder;MP3 encoder;and H.264 decoder. The time to find the Pareto front of each pipelined MPSoC was less than 4 minutes where design spaces had up to 1016 design points, illustrating the applicability of our approach.

关键词： Throughput

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FastFwd: An efficient hardware acceleration technique for trace-driven network-on-chip simulation 10

FastFwd: An efficient hardware acceleration technique for tr...

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Krishnaiah, Gummidipudi Silpa, B.V.N. Panda, Preeti Ranjan Kumar, Anshul Dept. of CSE IIT Delhi New Delhi India

ISBN: (纸本)9781605589053

We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speeds on host machines have motivated the need for hardware accelerators for speeding up the simulation. For example, simulation of applications with real life problem sizes could take weeks on a host machine. FPGA acceleration is a promising strategy for speeding up NoC simulations by several orders of magnitude. However, it is required to simulate a few billion network transactions of the application during NoC exploration, and this could still take tens of minutes even with an FPGA-based emulator. With the increasing complexity of architectures and applications, reducing emulation time is a key concern. We propose a technique, FastFwd, to minimize emulation time by efficiently identifying and eliminating redundant cycles during a trace-based NoC simulation. We have studied the implications of the additional FPGA hardware required for implementing our technique. A naïve implementation could lead to poor scalability and increase the required DRAM bandwidth, both of which ultimately impact the emulation speed negatively. We propose a hierarchical controller architecture to resolve the scalability issue, and a compressed representation of traces for mitigating the increased DRAM bandwidth requirement. Our experiments with several benchmarks have shown that the FPGA emulation with our technique reduces the average emulation time by a factor of 2 when compared to a conventional emulation.

关键词： Network-on-chip

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