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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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hardware-software codesign of fuzzy control systems using FPGAs

Hardware-software codesign of fuzzy control systems using FP...

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作者： Del Toro, E. Sánchez-Solano, S. Brox, M. Cabrera, A.J. CUJAE Ciudad de La Habana Cuba Sevilla Spain Dpto. Arquitectura de Computadores Electrónica Y Tecnología Electrónica Univ. Córdoba Spain Dpto. Automática Y Computación CUJAE Ciudad de La Habana Cuba

ISBN: (纸本)9789898425003

This paper describes a hardware/software codesign strategy for fuzzy control systems implementation using FPGAs. The main contribution of the paper consists of a methodology for joint development of hardware and software components intended for rapid and verifiable design of a fuzzy control system. The design flow combines specific tools for fuzzy inference systems included in the XFuzzy environment, simulation and modelling tools from Matlab and FPGA synthesis, and implementation tools provided by Xilinx. The advantages of this proposal are described in section 4 as it is used for the control system development of an autonomous vehicle.

关键词： Fuzzy control

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From ESL 2010 to ESL 2015 10

From ESL 2010 to ESL 2015

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Jeremiassen, Tor Martin, Grant Kogel, Tim Donlin, Adam Takach, Andres Chatha, Karam Texas Instruments United States Tensilica United States Synopsys United States Xilinx United States Mentor Graphics United States Arizona State University United States

ISBN: (纸本)9781605589053

In 2010, a wave of consolidation swept over the Electronic system Level (ESL) design industry. It brought ESL providers together with mainstream EDA houses and created opportunities for new ESL ventures. This paper contains short summaries of presentations in a special session focusing on the future of ESL. The session has two goals: the first is to present the state of the art in ESL tools and practice and, second, share a vision of the technical challenges that the next generation of ESL companies should address. The session includes a mix of perspectives from both ESL solution vendors and end-users and touches all all four ESL use cases: software virtual platforms, performance analysis, high level synthesis and verification.

关键词： High level synthesis

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hardware/software co-design for high performance computing: Challenges and opportunities

Hardware/software co-design for high performance computing: ...

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作者： Hu, X. Sharon Murphy, Richard C. Dosanjh, Sudip Olukotun, Kunle Poole, Stephen Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Scalable Computer Architecture Department Sandia National Laboratories Albuquerque NM United States Computer and Software Systems Department Sandia National Laboratories Albuquerque NM United States Department of Electrical Engineering Stanford University Stanford CA United States Computational Sciences Division Oak Ridge National Lab. Oak Ridge TN United States

ISBN: (纸本)9781605589053

This special session aims to introduce to the hardware/software codesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system design have traditionally been considered as two separate areas of research, they in fact share quite some common features, especially as CMOS devices continue along their scaling trends and the HPC community hits hard power and energy limits. Understanding the similarities and differences between the design practices adopted in the two areas will help bridge the two communities and lead to design tool developments benefiting both communities. © 2010 ACM.

关键词： hardware-software codesign

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Adaptive hardware-software Co-Design Platform for Fast Prototyping of Embedded systems

Adaptive Hardware-Software Co-Design Platform for Fast Proto...

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12th international conference on Optimization of Electrical and Electronic Equipment

作者： Oniga, Stefan Tisan, Alin Lung, Claudiu Buchman, Attila Orha, Ioan North Univ Dept Elect & Comp Engn Baia Mare Romania

ISBN: (纸本)9781424470198

This paper presents the hardware-software co-design platform based on FPGA developed for fast prototyping of embedded systems using hardware modules that can be easily connected and "driver" modules that can manage I/O devices and sensors basic behavior. Having this framework, adding of a new I/O peripheral needs only design and synthesis of an application specific VHDL or software module. Using neural networks (NN) to add learning capabilities and adaptive behavior is essential for an intelligent system and the use of FPGA is an important feature in terms of their hardware implementation. The designed architecture allows the insertion of intelligent interface based on neural networks created with this type of modules. This platform is based on low cost general purpose FPGA boards without need for hardware design.

关键词： Embedded systems Field programmable gate arrays Co-design intelligent interfaces hardware module Platform software module computer hardware design Intelligent systems PROTOTYPE Neural network IO Adaptive Behavior

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FPGA hardware design, simulation and synthesis for a independent component analysis algorithm using system-level design software

FPGA hardware design, simulation and synthesis for a indepen...

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international Multi-conference on Complexity, Informatics and Cybernetics, IMCIC 2010

作者： Da Silva, Alan Paulo Oliveira Guerreiro, Ana Maria Guimarães Neto, Adrião Duarte Dória Federal University of Rio Grande Do Norte UFRN - CT - PPgEEC Campus Universitário Centro de Tecnologia Natal RN59072-970 Brazil

ISBN: (纸本)9781934272886

In this work we proposed the design, simulation and synthesis of a hardware that performs the Independent Component Analysis (ICA) in a reconfigurable hardware platform, more specifically a FPGA. The simulation of the hardware was done by models implemented in Simulink environment and the synthesis was possible through the Altera system-level design software DSP Builder, that contains specific FPGA blocks that can be synthesized in hardware. In order to validate the hardware, manually generated data and real electroencephalogram signals were used in the experiments.

关键词： Field programmable gate arrays (FPGA)

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Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper

Enabling fast Network-on-Chip topology selection: an FPGA-ba...

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18th IEEE/IFIP international conference on VLSI and system-on-Chip

作者： Meloni, Paolo Secchi, Simone Raffo, Luigi Univ Cagliari Dept Elect & Elect Engn I-09124 Cagliari Italy

ISBN: (纸本)9781424464708

The complexity of modern interconnect architecture design requires highly accurate and rapid simulation environments. FPGA-based emulators have been proposed as an alternative to software cycle-accurate simulators, preserving maximum accuracy and reasonable simulation times. However, the potential speedup is reduced by the time overhead needed for RTL synthesis/implementation. This paper proposes runtime reconfiguration of the architecture to push the hardware emulation one step further, by reducing the number of FPGA implementation processes to be run. To this aim, this work presents an algorithm that synthesizes, for a set of candidate architectural configurations, a connection topology capable of reconfiguring itself via software to emulate all the design space points under evaluation. We present the actual reconfiguration algorithm, the CAD tools and the hardware mechanisms that implement it. The design capabilities provided by this approach are evaluated with a design space exploration case study.

关键词： FPGA-based runtime reconfigurable prototyper RTL synthesis-implementation circuit CAD design space points fast network-on-chip topology selection field programmable gate arrays modern interconnect architecture design network topology network-on-chip software cycle-accurate simulators time overhead

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8th ACM/IEEE international conference on Formal Methods and Models for codesign, MEMOCODE 2010

8th ACM/IEEE International Conference on Formal Methods and ...

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8th ACM/IEEE international conference on Formal Methods and Models for codesign, MEMOCODE 2010

ISBN: (纸本)9781424478859

The proceedings contain 28 papers. The topics discussed include: design contest overview: combined architecture for network stream categorization and intrusion detection (CANSCID);a regular expression matching using non-deterministic finite automation;numerical stability analysis of floating-point computations using software model checking;ATLAS: automatic term-level abstraction of RTL designs;a flexible schema for generating explanations in lazy theory propagation;a design flow based on modular refinement;systematic testing for control applications;compilation of imperative synchronous programs with refined clocks;minimizing back pressure for latency insensitive system synthesis;predictable multithreading of embedded applications using PRET-C;and power emulation: methodology and applications for HW/SW power optimization.

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An introduction to the systemC synthesis subset standard

An introduction to the SystemC synthesis subset standard

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作者： Coussy, Philippe Takach, Andres McNamara, Michael Meredith, Mike Université de Bretagne-Sud Rue de Saint Maude Lorient Cedex 56321 France Mentor Graphics 8005 SW Boeckman Rd. Wilsonville OR 97070 United States Cadence 2655 Seely Avenue San Jose CA 95134 United States Forte Design Systems 16150 NE 85th Street Redmond WA 98052 United States

ISBN: (纸本)9781605589053

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse [1][2][7]. © 2010 ACM.

关键词： High level synthesis

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Embedded systems Week 2010 - proceedings of the 8th IEEE/ACM/IFIP international conference on Compilers, Architecture and synthesis for Embedded systems, CODES+ISSS'10

Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM...

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6th Embedded systems Week, ESWEEK 2010 - 8th IEEE/ACM international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS'10

ISBN: (纸本)9781605589053

The proceedings contain 40 papers. The topics discussed include: rank based dynamic voltage and frequency scaling for tiled graphics processors;intermediate fabrics: virtual architectures for circuit portability and fast placement and routing;an elastic software cache with fast prefetching for motion compensation in video decoding;verification of dynamically reconfigurable embedded systems by model transformation rules;hardware/software optimization of error detection implementation for real-time embedded systems;scheduling garbage collection in real-time systems;hardware/software co-design for high performance computing: challenges and opportunities;exploring programming model-driven QoS support for NoC-based platforms;optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications;power aware SID-based simulator for embedded multicore DSP subsystems;and statistical approach in a system level methodology to deal with process variation.

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Architecture-aware graph-covering algorithm for custom instruction selection

Architecture-aware graph-covering algorithm for custom instr...

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5th international conference on Future Information Technology, FutureTech 2010

作者： Yazdanbakhsh, Amir Salehi, Mostafa E. Fakhraie, Sied Mehdi Nano Electronics Center of Excellence School of Electrical and Computer Engineering University of Tehran Tehran 14395-515 Iran

ISBN: (纸本)9781424469505

Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance demands of embedded applications. In recent customized processors, hardware in the form of new function units and the corresponding custom instructions are added to a core processor to meet the critical computational demands of a target application. This paper presents a new method for automatic selection of applicationspecific processor extensions. We demonstrate the effectiveness of this system across a range of application domains. Our investigations show that considering the architectural constraints in the custom instruction selection leads to improvements in the total performance of the application. Simulations based on domain-specific application benchmark suites show that with the proposed technique, up to 10% performance improvement can be achieved over the traditional graph covering method. © 2010 IEEE.

关键词： hardware-software codesign

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