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A system-level synthesis approach from formal application models to generic bus-based MPSoCs

A system-level synthesis approach from formal application mo...

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2010 10th international conference on Embedded Computer systems: Architectures, Modeling and Simulation, IC-SAMOS 2010

作者： Gladigau, Jens Gerstlauer, Andreas Haubelt, Christian Streubühr, Martin Teich, Jürgen Department of Computer Science University of Erlangen-Nuremberg Erlangen Germany Department of Electrical and Computer Engineering University of Texas at Austin Austin TX United States

ISBN: (纸本)9781424479382

system-level synthesis is the task of automatically implementing application models as hardware/software systems. It encompasses four basic sub tasks, namely decision making and refinement for both computation and communication. In the past, several system-level synthesis approaches have been proposed. However, it was shown that each of these approaches has drawbacks in at least one of the four sub tasks. In this paper, we present our efforts towards a comprehensive system-level synthesis by combining two academic system-level solutions into a seamless approach that automatically generates pin-accurate implementation-level models starting from a formal application model and generic MPSoC architecture templates. We analyze the system-level synthesis flow and define intermediate representations in terms of transaction level models that serve as link between existing tools. Furthermore, we present the automated transformation between models for combining two design flows. We demonstrate the combined flow on an industrial-strength example and show the benefits of fully automatic exploration and synthesis for rapid and early system-level design. ©2010 IEEE.

关键词： Decision making

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A holistic approach to Network-on-Chip synthesis

A holistic approach to Network-on-Chip synthesis

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作者： Leary, Glenn Chatha, Karam S. Arizona State University Department of CSE P.O. Box 875406 Tempe AZ 85287-5406 United States

ISBN: (纸本)9781605589053

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor system-on-Chip architectures. synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints. © 2010 ACM.

关键词： Network-on-chip

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Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming

Automatic parallelization of embedded software using hierarc...

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作者： Cordes, Daniel Marwedel, Peter Mallik, Arindam Informatik Centrum Dortmund Joseph-von-Fraunhofer-Str. 20 Dortmund Germany Imec Belgium Kapeldreef 75 Leuven Belgium

ISBN: (纸本)9781605589053

The last years have shown that there is no way to disregard the advantages provided by multiprocessor system-on-Chip (MPSoC) architectures in the embedded systems domain. Using multiple cores in a single system enables to close the gap between energy consumption, problems concerning heat dissipation, and computational power. Nevertheless, these benefits do not come for free. New challenges arise, if existing applications have to be ported to these multiprocessor platforms. One of the most ambitious tasks is to extract efficient parallelism from these existing sequential applications. Hence, many parallelization tools have been developed, most of them are extracting as much parallelism as possible, which is in general not the best choice for embedded systems with their limitations in hardware and software support. In contrast to previous approaches, we present a new automatic parallelization tool, tailored to the particular requirements of the resource constrained embedded systems. Therefore, this paper presents an algorithm which automatically steers the granularity of the generated tasks, with respect to architectural requirements and the overall execution time reduction. For this purpose, we exploit hierarchical task graphs to simplify a new integer linear programming based approach in order to split up sequential programs in an efficient way. Results on real-life benchmarks have shown that the presented approach is able to speed sequential applications up by a factor of up to 3.7 on a four core MPSoC architecture. © 2010 ACM.

关键词： Embedded systems

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Designing application specific circuits with concurrent C# programs

Designing application specific circuits with concurrent C# p...

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ACM and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： David Greaves Satnam Singh Computer Laboratory University of Cambridge Cambridge UK Microsoft Research Cambridge Cambridge UK

This paper presents an investigation into the possibility of using a regular concurrent programming language for modeling and implementing digital circuits. Some of the reasons for using an existing language include the ability to use existing compilers and analysis tools for circuit design and verification. Another important reason is the ever increasing need to model complete systems that comprise interacting software and hardware in a single framework which facilitates easier migration of sub-components between hardware and software implementations compared to multi-model approaches. To this end we present the design of the Kiwi system which models digital circuits with concurrent programs using a standard library in C# for multi-threaded programming. Kiwi models can be executed using a regular C# compiler. Also, the compiled bytecode can be automatically converted into circuits using our Kiwi hardware synthesis system.

关键词： hardware Integrated circuit modeling Message systems Biological system modeling Concurrent computing software Monitoring

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A driver-to-infrastructure interaction system for motorcycles based on smartphone

A driver-to-infrastructure interaction system for motorcycle...

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international IEEE conference on Intelligent Transportation systems

作者： Manzoni, Vincenzo Corti, Andrea Spelta, Cristiano Savaresi, Sergio M. Politecnico di Milano Dipartimento di Elettronica e Informazione 20133 Milan Italy Università degli Studi di Bergamo Dipartimento di Ingegneria dell'Informazione e Metodi Matematici 24044 Dalmine Italy

ISBN: (纸本)9781424476572

This paper concerns the definition and implementation of an add-on interaction system for motorcycles. The system is a vehicle-to-driver communication system and a driver-to-infrastructure communication system, based on a smartphone core and a wireless Bluetooth medium. The system is devoted to increase the safety level of a motorcycle and it is constituted by a vehicle with a CAN bus, a compact embedded electronic implementing a CAN-to-Bluetooth gateway, a smartphone and a Bluetooth helmet. The driver-to-vehicle system is based on an audio interaction located at helmet level. The driver-to- infrastructure is represented by communication via a HTTP protocol. The vocal synthesis, the speech recognition, and the web gateway are resident on the smartphone. This work presents the general hardware and software architecture and some specific web-oriented implementation. An evaluation of the critical aspects of the system is also provided. ©2010 IEEE.

关键词： Smartphones

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A codesign synthesis from an MPEG-4 decoder dataflow description

A codesign synthesis from an MPEG-4 decoder dataflow descrip...

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IEEE international Symposium on Circuits and systems (ISCAS)

作者： Nicolas Siret Ismail Sabry Jean Francois Nezan Mickael Raulet IETR/INSA UMR CNRS 6164 Rennes France Lead Tech Design Rennes France

The elaboration of new and innovative systems such as MPSoC (Multiprocessor system on Chip) which are made up of multiple processors, memories and IPs lies on the designers to achieve a complex codesign work. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. Our approach to design such systems is based on the usage of a high level of abstraction language called RVC CAL. This language is dataflow oriented and thus points out the concurrency and parallelism of algorithms. Moreover CAL is supported by the OpenDF simulator and by two code generators called CAL2C (software generator) and CAL2HDL (hardware generator). The MPEG expert group has recently elaborated the Reconfigurable Video Coding (RVC) standard which defines the RVC CAL language as reference for MPEG video decoder descriptions. This paper introduces the opportunities to design an innovative system involving hardware and software IPs, embedded processors and memories from a CAL model. Practical results on a FPGA are provided with a codesign solution of an MPEG4 Simple Profile (SP).

关键词： MPEG 4 Standard Decoding hardware Video coding Code standards Standards development Embedded software Field programmable gate arrays Codecs MPEG standards

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FastFwd: An efficient hardware acceleration technique for trace-driven network-on-chip simulation

FastFwd: An efficient hardware acceleration technique for tr...

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作者： Krishnaiah, Gummidipudi Silpa, B.V.N. Panda, Preeti Ranjan Kumar, Anshul Dept. of CSE IIT Delhi New Delhi India

ISBN: (纸本)9781605589053

We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speeds on host machines have motivated the need for hardware accelerators for speeding up the simulation. For example, simulation of applications with real life problem sizes could take weeks on a host machine. FPGA acceleration is a promising strategy for speeding up NoC simulations by several orders of magnitude. However, it is required to simulate a few billion network transactions of the application during NoC exploration, and this could still take tens of minutes even with an FPGA-based emulator. With the increasing complexity of architectures and applications, reducing emulation time is a key concern. We propose a technique, FastFwd, to minimize emulation time by efficiently identifying and eliminating redundant cycles during a trace-based NoC simulation. We have studied the implications of the additional FPGA hardware required for implementing our technique. A naïve implementation could lead to poor scalability and increase the required DRAM bandwidth, both of which ultimately impact the emulation speed negatively. We propose a hierarchical controller architecture to resolve the scalability issue, and a compressed representation of traces for mitigating the increased DRAM bandwidth requirement. Our experiments with several benchmarks have shown that the FPGA emulation with our technique reduces the average emulation time by a factor of 2 when compared to a conventional emulation. © 2010 ACM.

关键词： Network-on-chip

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system-level reliability modeling for MPSoCs

System-level reliability modeling for MPSoCs

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作者： Xiang, Yun Chantem, Thidapat Dick, Robert P. Hu, X. Sharon Shang, Li EECS Department University of Michigan Ann Arbor MI 48109 United States CSE Department University of Notre Dame Notre Dame IN 46556 United States ECE Department University of Colorado Boulder CO 80309 United States

ISBN: (纸本)9781605589053

The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Accurate and fast reliability modeling is a primary challenge in the design and optimization of reliable MPSoCs. This paper presents a reliability modeling framework that integrates device-, component-, and system-level models. This framework contains modules for electromigration, time-dependent dielectric breakdown, stress migration, and variable-amplitude thermal cycling. A new statistical reliability distribution is proposed for accurate characterization of components containing too few devices for an extreme value distribution to be appropriate. A hierarchical system-level survival lattice based Monte Carlo technique is used to estimate the temporal fault distributions of MPSoCs that use arbitrary static and dynamic reliability-enhancing redundancy schemes. Physical process variation, which may have a significant impact on MPSoC reliability, is considered in the model. The proposed modeling technique has 5% average error in mean time to failure and reduces simulation time by nearly 3 orders of magnitude relative to a non-hierarchical Monte Carlo technique. © 2010 ACM.

关键词： Hierarchical systems

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A hardware-efficient frequency domain correlator architecture for acquisition stage in GPS

A hardware-efficient frequency domain correlator architectur...

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international conference on Reconfigurable Computing and FPGAs

作者： Romero-Aguirre, E. Parra-Michel, R. Longoria-Gandara, O. Aguirre-Hernández, M. Dept. of Electrical Engineering CINVESTAV-IPN Mexico Electronics Systems and Computer Sc. Department ITESO Mexico Comms. Research Center Mexico Intel Corp. Jalisco Mexico

ISBN: (纸本)9780769543147

A frequency domain correlator (FDC) with low-complexity architecture is proposed. This signal processing module is part of FFT-based acquisition stage of a global position system (GPS). The FDC is based on a single reconfigurable core capable of computing both decimation in frequency radix-2 (DIF-2) fast Fourier transform (FFT) and decimation in time radix-2 (DIT-2) inverse fast Fourier transform (IFFT). The proposed FDC reuses the reconfigurable core together with appropriate decimation choice, providing an improvement in resource management while avoiding any additional reorder data hardware. Additionally, the FDC architecture shows a great flexibility due to three levels of parameterization which allows to fix the number of complex input samples, data width and word format. The architecture has been implemented in Altera Cyclone II and Xilinx Virtex II Pro for N-points correlation with different word lengths. The simulation and synthesis results shows that the FDC is suitable for performing acquisition stage in GPS, enabling its utilization in software define radios. © 2010 IEEE.

关键词： Global positioning system

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Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications

Optimal synthesis of latency and throughput constrained pipe...

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作者： Javaid, Haris He, Xin Ignjatovic, Aleksander Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

ISBN: (纸本)9781605589053

A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specific Instruction set Processors (ASIPs), called a pipelined MPSoC. The latency and throughput requirements of streaming applications put constraints on the design of such a pipelined MPSoC, where each ASIP has a number of available configurations differing by additional instructions, and instruction and data cache sizes. Thus, the design space of a pipelined MPSoC is all the possible combinations of ASIP configurations (design points). In this paper, a methodology is proposed to optimize the area of a pipelined MPSoC under a latency or a throughput constraint. The final design point is a set of ASIP configurations with one configuration for each ASIP. We proposed an Integer Linear Programming (ILP) based solution to the area optimization problem under a latency constraint, and an algorithm for optimization of pipelined MPSoC area under a throughput constraint. The proposed solutions were evaluated using four streaming applications: JPEG encoder;JPEG decoder;MP3 encoder;and H.264 decoder. The time to find the Pareto front of each pipelined MPSoC was less than 4 minutes where design spaces had up to 1016 design points, illustrating the applicability of our approach. © 2010 ACM.

关键词： Throughput

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