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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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Embedded systems Week 2010 - proceedings of the 8th IEEE/ACM/IFIP international conference on Compilers, Architecture and synthesis for Embedded systems, CODES+ISSS'2010: Foreword

Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM...

引用

Embedded systems Week 2010 - proceedings of the 8th IEEE/ACM/IFIP international conference on Compilers, Architecture and synthesis for Embedded systems, CODES+ISSS'2010 2010年 iii页

作者： Givargis, Tony Donlin, Adam

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Embedded systems Week 2010 - proceedings of the 8th IEEE/ACM/IFIP international conference on Compilers, Architecture and synthesis for Embedded systems, CODES+ISSS'2010: Welcome message from the general chairs

Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM...

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Embedded systems Week 2010 - proceedings of the 8th IEEE/ACM/IFIP international conference on Compilers, Architecture and synthesis for Embedded systems, CODES+ISSS'2010 2010年 ii页

作者： Sciuto, Donatella Chakraborty, Samarjit

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7th IFIP TC 10 Working conference on Distributed and Parallel Embedded systems, DIPES 2010 and 3rd IFIP TC 10 international conference on Biologically-Inspired Collaborative Computing, BICC 2010 held as part of the 21st IFIP World Computer Congress, WCC 2010

7th IFIP TC 10 Working Conference on Distributed and Paralle...

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7th IFIP TC 10 Working conference on Distributed and Parallel Embedded systems, DIPES 2010 and 3rd IFIP TC 10 international conference on Biologically-Inspired Collaborative Computing, BICC 2010 Held as Part of 21st IFIP World Computer Congress, WCC 2010

ISBN: (纸本)9783642152337

The proceedings contain 29 papers. The special focus in this conference is on Distributed, Parallel and Biologically Inspired systems. The topics include: Mastering conflicting trends in embedded systems design;a language for heterogeneous computations;scenario-based modeling in industrial information systems;an entirely model-based framework for hardware design and simulation;extending the standard execution model of UML for real-time systems;task migration for fault-tolerant flexray networks;flexible and dynamic replication control for interdependent distributed real-time embedded systems;generation of executable testbenches from natural language requirement specifications for embedded real-time systems;model checking of concurrent algorithms;integrate online model checking into distributed reconfigurable system on chip with adaptable OS services;efficient mutation-analysis coverage for constrained random verification;generating VHDL source code from UML models of embedded systems;a rapid, architectural simulation and synthesis framework for embedded processors;a mixed level simulation environment for stepwise RTOS software refinement;dependency-driven distribution of synchronous programs;distributed resource-aware scheduling for multi-core architectures with system C;robust partitioned scheduling for real-time multiprocessor systems;an infrastructure for flexible runtime reconfigurable multi-microcontroller systems;feature selection for classification using an ant system approach;a collaborative decision support model for marine safety and security operations and collaborating and learning predators on a pursuit scenario.

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MARKOVIAN PERFORMABILITY MODELING FOR hardware-software system

MARKOVIAN PERFORMABILITY MODELING FOR HARDWARE-SOFTWARE SYST...

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15th ISSAT international conference on Reliability and Quality in Design

作者： Takahashi, Junichi Tokuno, Koichi Yamada, Shigeru Tottori Univ Grad Sch Engn Tottori 6808552 Japan

ISBN: (纸本)9780976348658

In this paper, we discuss the performability evaluation model for tire computer-based system, introducing the concept of hardware/software codesign. We assume that the computer system consists of one hardware and one software subsystem and consider both of hardware and software failure/restoration characteristics. In particular, the reliability growth process, the upward tendency of difficulty in debugging, and the imperfect debugging environment are described for the software subsystem. Assuming that the system can process the multiple tasks simultaneously and that, the arrival process of tire tasks follows a nonhomogeneous Poisson process, we analyze the distribution of the number of tasks whose processes can be completed within the prespecified processing time limit with the infinite server queueing theory. We derive several performability measures considering the real-time property, which are given as the functions of time and the number of debugging activities. Finally we illustrate several numerical examples of the measures to investigate the impact of hardware/software failure/restoration characteristics on the system performability evaluation.

关键词： hardware/software codesign performability evaluation Markov process software reliability growth infinite-server queueing model

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A Low Power Biomedical Signal Processor ASIC Based on hardware software codesign

A Low Power Biomedical Signal Processor ASIC Based on Hardwa...

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Annual international conference of the IEEE-Engineering-in-Medicine-and-Biology-Society

作者： Nie, Z. D. Wang, L. Chen, W. G. Zhang, T. Zhang, Y. T. Institute of Biomedical and Health Engineering (IBHE) Shenzhen Institute of Advanced Technology (SIAT) China

ISBN: (纸本)9781424432950

A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 mu m mixed-signal CMOS 1P6M technology. The die area measures 5,000 mu m x 2,350 mu m. The power consumption was approximately 3.6 mW at 1.8V power supply and 1MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

关键词： Fast Fourier transforms

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Lane Detection system Based on software and hardware codesign

Lane Detection System Based on Software and Hardware Codesig...

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4th international conference on Autonomous Robots and Agents

作者： Jeng, Ming-Jer Guo, Chung-Yen Shiau, Bo-Cheng Chang, Liann-Be Hsiao, Pei-Yung Chang Gung Univ Dept Elect Engn Tao Yuan Taiwan Natl Kaohsiung Univ Dept Elect Engn Kaohsiung Taiwan

ISBN: (纸本)9781424427123

In this paper, we present a lane detection system (LDS) based on software and hardware codesign. In combining both hardware and software designs, it can achieve a real time lane detection within a processing time of less than 50ms. The hardware implemented by FPGA chip captures the lane image from CCD camera within a time less 10ms, which is faster than by soft-ware captures. In software design, the global edge detection is able to transfer the gray level image to binary pattern and show the edge of the object. Then, using this binary pattern rind out the traffic lane location with following algorithm like the peak-finding and grouping, edge connecting, lane segment combination, lane boundaries selection. The lane departure warning algorithm detects the vehicle whether in traffic lane and judges whether sends out the warning. Experimental results demonstrate a quite good accuracy in lane detection whether at day or night condition.

关键词： Lane detection system Global edge detector Lane departure warning algorithm

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A HW/SW Co-design Methodology: An Accurate Power Efficiency Model and Design Metrics for Embedded system

A HW/SW Co-design Methodology: An Accurate Power Efficiency ...

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3rd international Workshop on e-Activity (IWEA2009)/10th ACIS international conference on software Engineering Artificial Intelligence, Networking and Parallel/Distributed Computing

作者： Iftikhar, Khan Jeong, Taikyeong Ted Park, Gyungleen Ambler, Anthony P. Myongji Univ Dept Commun Eng Seoul South Korea Jeju Natl Univ Dept Comp Stat Jeju-do South Korea Univ Texas Austin Dept Elect & Comp Eng Austin TX 78712 USA

ISBN: (纸本)9780769536422

Low-power embedded system design has become extremely important in the most recent years. To fulfill system-level design requirements and time-to-market constraints, a power-driven methodology is essential during embedded system design. The aim of this paper is to introduce accurate and efficient power metrics included in a hardware/software (HW/SW) co-design environment to show the system-level partitioning and design. In order to verify the design effectiveness of hardware/software co-design synthesis, we consider the digital power dissipation methodology and its power reduction techniques. To maximize the performance of system, we developed hierarchical design technique and co-design synthesis for power efficient HW/SW co-design process. In the end, we provided simulation results for single circuit with new design vs. circuit integration with hierarchical power efficiency system (HPES), multiple circuits with new design vs. circuit integration with HPES, new design and no load vs. circuit integration with HPES, new design with load vs. circuit integration with HPES.

关键词： Embedded systems hardware/software codesign low-power power metrics

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A Novel hardware-software codesign of network protocol stacks on a SoC platform

A Novel hardware-software codesign of network protocol stack...

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2009 18th international conference on Computer Communications and Networks, ICCCN 2009

作者： Kim, Youngmann Kim, Taehoon Park, E.K. Tak, Sungwoo School of Computer Science and Engineering Pusan National University Busan Korea Republic of School of Computing and Engineering University of Missouri Busan Kansas City MO United States

ISBN: (纸本)9781424445813

In this paper, we propose a novel hardware-software codesign technique of network protocol stacks on a SoC (system on Chip) platform for providing the QoS (Quality of Service) functionality. We address that the codesign should guarantee the real-time performance of periodic packets and minimize the average response time of aperiodic packets in order to provide the QoS functionality. We present the following three mechanisms to resolve this issue: 1) task decomposition technique of a network protocol suite into hardware and software tasks, 2) a communication channel between heterogeneous tasks, 3) finegrained and coarse-grained real-time processing simultaneously for application-specific real-time requirements. A case study based on experiments is conducted to illustrate the efficiency of the proposed technique by implementing it on the commercial SoC platform embedded with the Altera's Excalibur EPXA4 including ARM922T core and 400K gates of programmable logic. ©2009 IEEE.

关键词： Programmable logic controllers

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codesign of embedded systems with process/module level real-time deadlines

Codesign of embedded systems with process/module level real-...

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7th IEEE/IFIP international conference on Embedded and Ubiquitous Computing, EUC 2009

作者： Khan, Gul N. Awwal, Anika Electrical and Computer Engineering Ryerson University 350 Victoria Street Toronto ON M5B 2K3 Canada

ISBN: (纸本)9780769538235

We present a codesign method that synthesizes heterogeneous multiple processing element embedded systems with real-time constraints. hardware/software partitioning is performed using Genetic algorithm. The proposed cosynthesis method explores various target architectures and one of them is an optimized architecture of the system. The method is capable of producing feasible solutions for large-scale real-time embedded systems. Non-preemptive and conditional preemptive scheduling techniques are employed that can deal with module (application) and process level deadlines. The method also supports communicationlink allocation and communication events scheduling and the method also achieves better CPU utilization. © 2009 IEEE.

关键词： Real time systems

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Particle Swarm Optimization for Run-Time Task Decomposition and Scheduling in Evolvable MPSoC

Particle Swarm Optimization for Run-Time Task Decomposition ...

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international conference on Computer Engineering and Technology

作者： Vakili, Shervin Fakhraie, S. Mehdi Mohammadi, Siamak Ahmadi, Ali Univ Tehran Sch Elect & Comp Engn Silicon Intelligence & VLSI Signal Proc Lab Tehran Iran

ISBN: (纸本)9780769535210

Decomposition and scheduling are two major challenges in hardware and software developments of multiprocessor systems. The introduced EvoMT (Evolvable Multi-Processor) is a novel NoC-based homogeneous MPSoC system that performs decomposition and scheduling using evolutionary algorithms at run-time. A hardware genetic core was used in first version of this platform to perform these two tasks. This core tries to find an efficient solution for decomposition and scheduling of the target application among available computational resources. This paper presents the new version of this system in which a hardware Particle Swarm Optimization (PSO) core is exploited to perform evolutionary decomposition and scheduling. The principle of operation and architecture of the EvoMP platform and the PSO core is briefly explained in this paper. The simulation and synthesis results of this PSO-based EvoMT is also presented and compared with prior genetic-base approach.

关键词： MPSoC Particle Swarm Optimization Particle swarm optimization Runtime Computer hardware task decomposition computer software

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