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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1551 条记录，以下是51-60 订阅

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Conflict analysis in multiprocess synthesis for optimized system integration 05

Conflict analysis in multiprocess synthesis for optimized sy...

引用

international conference on hardware/software codesign and system synthesis

作者： Bringmann, O Siebenborn, A Rosenstiel, W FZI Forschungszentrum Informat D-76131 Karlsruhe Germany

ISBN: (纸本)1595931619

This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing architectural synthesis approaches in order to apply global optimization techniques across process bounds for shared system resources (e.g. memories, busses, global ALUs) during scheduling and binding. This allows an area efficient implementation of un-timed or cycle-fixed multiprocess specifications at RT or algorithmic level of abstraction. Furthermore, this approach supports environment-oriented synthesis for optimized module integration by scheduling accesses to global resources with respect to the access schedules of other modules communicating to the same global resources. As a result, dynamic access conflicts can be avoided by construction, and hence, there is no need for dynamic arbitration of bus and memory accesses with potentially unpredictable timing behavior.

关键词： behavioral synthesis system level design systems-on-chip scheduling binding concurrent systems

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Special Session Paper: An Efficient hardware Design for Cerebellar Models using Approximate Circuits 12

Special Session Paper: An Efficient Hardware Design for Cere...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Jiang, Honglan Liu, Leibo Han, Jie Univ Alberta Edmonton AB Canada Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： Cerebellar model approximate circuits multiplier adder

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Techniques for Design Analysis and Modification Based on ASAP Model Work-in-Progress

Techniques for Design Analysis and Modification Based on ASA...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Du, Ke Domas, Stephane Lenczner, Michel Univ Bourgogne Franche Comte FEMTO ST Inst UMR 6174 CNRS Belfort France

ISBN: (纸本)9781728191980

In the domain of model-based design, the main challenge is to provide a model with a set of conditions and algorithms to ensure that the designed system produces correct results. A dataflow based model called Actors with Stretchable Access Patterns (ASAP) has been recently proposed, which takes the behavior of functional blocks on real architectures, especially FPGAs, into account. In this work, we present the framework of techniques to analyze the correctness of designs based on the ASAP model and to determine a set of modifications that must be applied to faulty cases to ensure the conformance of all actors. The principles are illustrated by a realistic application.

关键词： ASAP FPGA model-based design system analysis EDA

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Work-in-Progress: Lark: A Learned Secondary Index Toward LSM-tree for Resource-Constrained Embedded Storage systems

Work-in-Progress: Lark: A Learned Secondary Index Toward LSM...

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ACM/IEEE international conference on hardware/software codesign and system synthesis part of the Embedded systems Week (ESWEEK)

作者： Yuan, Jianan Liu, Huan Wu, Shangyu Lin, Yiquan Wang, Tiantian Ma, Chenlin Mao, Rui Wang, Yi Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Peoples R China City Univ Hong Kong Memory Syst & IoT Lab Hong Kong Peoples R China

ISBN: (数字)9781665472944

ISBN: (纸本)9781665472944

LSM-tree-based key-value stores are popular in embedded storage systems. With the growing demands of data analysis, the secondary index is created to support non-primary-key lookups. However, the lookup efficiency and space consumption of secondary index remain for further optimization. Inspired by the learned index, this paper presents Lark, a learned secondary index toward LSM-tree for resource-constrained embedded storage systems. Lark employs machine learning to speed up the non-primary-key queries and compress secondary indexes. Our preliminary evaluations show that, in comparison with traditional secondary index schemes, Lark achieves better lookup performance with less space consumption.

关键词： Secondary index LSM-tree machine learning

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hardware/software co-design for high performance computing: Challenges and opportunities 10

Hardware/software co-design for high performance computing: ...

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proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Hu, X. Sharon Murphy, Richard C. Dosanjh, Sudip Olukotun, Kunle Poole, Stephen Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Scalable Computer Architecture Department Sandia National Laboratories Albuquerque NM United States Computer and Software Systems Department Sandia National Laboratories Albuquerque NM United States Department of Electrical Engineering Stanford University Stanford CA United States Computational Sciences Division Oak Ridge National Lab Oak Ridge TN United States

ISBN: (纸本)9781605589053

This special session aims to introduce to the hardware/software codesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system design have traditionally been considered as two separate areas of research, they in fact share quite some common features, especially as CMOS devices continue along their scaling trends and the HPC community hits hard power and energy limits. Understanding the similarities and differences between the design practices adopted in the two areas will help bridge the two communities and lead to design tool developments benefiting both communities.

关键词： hardware-software codesign

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Extending the systemC synthesis subset by object-oriented features

Extending the SystemC synthesis subset by object-oriented fe...

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1st IEEE/ACM/IFIP international conference on Hardward/software codesign and system synthesis

作者： Grimpe, E Oppenheimer, F OFFIS Res Inst D-26121 Oldenburg Germany

ISBN: (纸本)1581137427

In this article we present an approach to object-oriented hardware design and synthesis based on systemC. We will give an introduction to an extended systemC synthesis subset which we propose, and;in particular, its object-oriented features. We will also briefly outline our basic synthesis concepts for object-oriented hardware specifications. Finally we will present some examples for the application of the extended synthesis subset, which are directly processable by a first synthesis tool prototype which we have developed for this purpose.

关键词： systemC C/C plus plus based design hardware description language hardware synthesis system level design object-orientation high-level synthesis

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Work-in-Progress: Heterogeneous Redundancy to Address Performance and Cost in Multi-core SIMT 12

Work-in-Progress: Heterogeneous Redundancy to Address Perfor...

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international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Naghashi, M. Mozafari, S. H. Hessabi, S. Sharif Univ Technol Tehran Iran McGill Univ Montreal PQ Canada

ISBN: (纸本)9781450351850

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. In this work, we investigate adding heterogeneous hot redundancy (i.e., the architecture of redundant hot cores is diferent from the baseline cores) to improve the cost and performance of multicore single-instruction, multiple-thread (SIMT) architectures. We propose to utilize x86 out of order (OoO) cores as redundancy in SIMT processors. In this case, dice with unused functional redundancies can beneit from two types of processing cores (OoO and SM).

关键词： Manufacturability system-level design redundancy

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codesign-extended applications

Codesign-extended applications

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10th international Symposium on hardware/software codesign (CODES 2002)

作者： Grattan, B Stitt, G Vahid, F Univ Calif Riverside Dept Elect Engn Riverside CA 92521 USA

ISBN: (纸本)1581135424

We challenge the widespread assumption that an embedded system's functionality can be captured in a single specification and then partitioned among software and custom hardware processors. The specification of some functions in software is very different from the specification of the same function in hardware- too different to conceive of automatically deriving one from the other. We illustrate this concept using a digital camera example. We introduce the idea of codesign-extended applications to deal with the situation, wherein critical functions are written in multiple versions, and integrated such that simple compiler/synthesis flags instantiate a particular version along with the necessary control and communication behavior. By capturing a specification as a codesign-extended application, a designer enables smooth migration among platforms with increasing amounts of on-chip configurable logic.

关键词： hardware/software partitioning hardware/software cospecification configurable logic system-on-a-chip platform-based design

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software system for parsing signal processing tasks over multiple heterogeneous processors

Software system for parsing signal processing tasks over mul...

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conference on Advanced Signal Processing Algorithms

作者： WARSHAWSKY, EH JRS RES LABS INC ORANGECA 92665

ISBN: (纸本)0819419222

A design automation toolset of great applicability to the signal processing system design community is described herein, the JRS NetSyn product. NetSyn provides facilities for building and maintaining libraries of reusable hardware and software parts. The NetSyn methodology supports hardware/software codesign and tradeoffs and the distribution of software functions to processing elements in accordance with selected optimization objectives. NetSyn utilizes VHDL, Ada, and ANSI C standard languages and related tools. It facilities software reuse by porting application systems to alternative architectures. The paper presents some of the underlying concepts of NetSyn and then describes the functionality of the toolset in some detail.

关键词： DESIGN AUTOMATION synthesis SIMULATION hardware software codesign

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Resource sharing estimation by Petri nets in PISH hardware/software co-design system

Resource sharing estimation by Petri nets in PISH hardware/s...

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IEEE international conference on systems, Man and Cybernetics

作者： Maciel, P Barros, E Silva, M Cruz, F Univ Fed Pernambuco Ctr Informat BR-50740540 Recife PE Brazil

ISBN: (纸本)0780365836

This work presents two approaches for computing the number of functional units in hardware/software codesign context, The proposed hardware/software codesign framework uses Petri net as common formalism for performing quantitative and qualitative analysis. The use of Petri net as an intermediate format allows to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. This paper is devoted to describe the algorithms for functional unit estimation. This work also proposes a method of extending the Petri net model in order to take into account causal constraints provided by the designers. However, an overview of the general hardware/software codesign method is also presented.

关键词： Petri nets

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