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system-level mitigation of WID leakage power variability using body-bias islands 08

System-level mitigation of WID leakage power variability usi...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Garg, Siddharth Marculescu, Diana Dept. of Electrical and Computer Engineering Carnegie Mellon University United States

ISBN: (纸本)9781605584706

Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of "body-bias islands," each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation framework to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed framework in reducing the mean and standard deviation of leakage power dissipation compared to a baseline system without ABB. At the same time, the proposed techniques provide significant runtime improvements over a previously proposed Monte-Carlo based technique while providing similar reductions in leakage power dissipation. Copyright 2008 ACM.

关键词： Bias voltage

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Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors

Yield maximization for system-level task assignment and conf...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Singhal, Love Oh, Sejong Bozorgzadeh, Eli Center for Embeddded Computer Systems University of California Irvine United States Korea Advanced Institute of Science and Technology Daejeon Korea Republic of

ISBN: (纸本)9781605584706

Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development time, and potentially high performance under constraints and challenges driven by applications. An important design challenge at 45nm for multi-core system is manufacturing process variation. Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints. Due to interdependency between processor configuration selection and task allocation and its impact on yield and latency constraints, we tackle both problems simultaneously. In this paper, we propose the problem of task allocation and configuration selection for yield optimization. We prove the problem is NP-hard and propose an optimal pseudo-polynomial on Serial-Parallel graphs. We target streaming applications in pipelined reconfigurable multiprocessor systems. We provide a case study of configurable Leon processors as the cores implemented on FPGA. Results show that proposed problem could result in significant improvement of the timing yield of the system by exploiting extra slack on tasks. Copyright 2008 ACM.

关键词： Optimization

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Co-simulation of networked embedded system: Verification approach

Co-simulation of networked embedded system: Verification app...

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2nd IEEE international conference on Secure system Integration and Reliability Improvement, SSIRI 2008

作者： Damle, Nikhil Keskar, A.G. Department of Electronics Engineering Visvesvaraya National Institute of Technology Nagpur India

ISBN: (纸本)9780769532660

The paper gives an extension to the existing approach to hardware/software codesign of embedded systems by including the missed out network element commonly seen in the today's embedded systems. The approach tries to provide a verification platform for networked embedded system. Virtual system modeling of networks & their interaction with hardware-software is the key issue in the heterogeneous co-simulation of networked embedded system. © 2008 IEEE.

关键词： Embedded systems

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Reliable performance analysis of a multicore multithreaded system-on-chip 08

Reliable performance analysis of a multicore multithreaded s...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Schliecker, Simon Negrean, Mircea Nicolescu, Gabriela Paulin, Pierre Ernst, Rolf Technische Universität Braunschweig Germany Ecole Polytechnique de Montreal Canada ST Microelectronics Ottawa Canada

ISBN: (纸本)9781605584706

Formal performance analysis is now regularly applied in the design of distributed embedded systems such as automotive electronics, where it greatly contributes to an improved predictability and platform robustness of complex networked systems. Even though it might be highly beneficial also in MpSoC design, formal performance analysis could not easily be applied so far, because the classical task communication model does not cover processor-memory traffic, which is an integral part of MpSoC timing. Introducing memory accesses as individual transactions under the classical model has shown to be inefficient, and previous approaches work well only under strict orthogonalization of different traffic streams. Recent research has presented extensions of the classical task model and a corresponding analysis that covers performance implications of shared memory traffic. In this paper we present a multithreaded multiprocessors platform and multimedia application. We conduct performance analysis using the new analysis options and specifically benchmark the quality of the available approach. Our experiments show that corner case coverage can now be supplied with a very high accuracy, allowing to quickly investigate architectural alternatives. Copyright 2008 ACM.

关键词： system-on-chip

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Intra- and inter-processor hybrid performance modeling for MPSoC architectures 08

Intra- and inter-processor hybrid performance modeling for M...

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Embedded systems Week 2008 - 6th IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Ophelders, Frank E.B. Chakraborty, Samarjit Corporaal, Henk Department of Electrical Engineering Technische Universiteit Eindhoven Netherlands Department of Computer Science National University of Singapore Singapore

ISBN: (纸本)9781605584706

The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid performance model-ing techniques. Here, the idea is to apply different modeling and analysis techniques to different subsystems/components of an ar-chitecture/application. Such hybrid techniques often turn out to be more efficient and accurate compared to relying on a single analy-sis technique for the entire system. However, the challenge asso-ciated with this approach is to combine the different analysis re-sults effectively to obtain conservative performance estimates for the entire system. In this paper we study a hybrid scheme where certain system components are simulated (e.g. using instruction set simulators), whereas others are analyzed using a formal tech-nique called Real-Time Calculus (RTC). The main novelty of our approach stems from our use of this hybrid technique even for mul-tiple tasks mapped onto a single processing element. In contrast to this, previous approaches relied on either full simulation or RTC-based analysis for an entire architectural component (e.g. a proces-sor or a bus). The techniques we develop in this paper therefore al-low for both intra- and inter-processor hybrid performance model-ing and show how the different analysis results can be combined to efficiently obtain tight performance estimates for complex MPSoC architectures. We demonstrate the usefulness of this approach us-ing an MPEG-2 decoder application that is partitioned and mapped onto two processing elements connected by FIFO buffers. Copyright 2008 ACM.

关键词： system-on-chip

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hardware/software Co-synthesis of Distributed Embedded systems Using Genetic Programming

Hardware/Software Co-synthesis of Distributed Embedded Syste...

引用

8th international conference on Evolvable systems

作者： Deniziak, Stanislaw Gorski, Adam Krakow Tech Univ Dept Comp Engn PL-31155 Krakow Poland

ISBN: (纸本)9783540858560

This work presents a novel approach to hardware-software co-synthesis of distributed embedded systems, based on the developlmental genetic programming. Unlike the other genetic approaches where chromosomes represent solutions, in our method chromosomes represent system construction procedures. Thus, not the system architecture but the co-synthesis process is evolved. Finally a tree describing a construction of a final solution is obtained. The optimization process will be illustrated with examples. According to Our best knowledge it is the first DGP approach that deals with the hardware-software co-synthesis.

关键词： Genetic programming hardware/software co-design

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Vision: Testing of mechatronics software using agile simulation

Vision: Testing of mechatronics software using agile simulat...

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3rd international Workshop on Automation of software Test, AST 2008, held in Conjunction with the 30th international conference on software Engineering, ICSE 2008

作者： Masticola, Stephen P. Gall, Michael Siemens Corporate Research 755 College Road East Princeton NJ 08540 United States

ISBN: (纸本)9781605580302

Mechatronics is the practice of creating systems that synergize electrical, mechanical, and software technology. With few exceptions, testing software that is embedded in mechatronics systems has historically been done only with the hardware in the loop (HIL). There are many disadvantages to HIL testing, including cost, schedule delays, and resource bottlenecks. Ironically, cost and schedule delays are also often seen by technical managers as impediments to simulating the mechatronics hardware. We present a vision for agile simulation, with the intent to lower the cost and time barriers of simulating mechatronics hardware to test software. Some key ideas include: focus on validating the software alone, rather than the entire system;doing the minimum amount of dynamic modeling needed to test the software;work even with legacy systems that might not have been designed with testability in mind;leverage existing tools wherever possible;support stubbing out the hardware using agile techniques such as refactoring and test-driven development. Copyright 2008 ACM.

关键词： hardware-software codesign

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Architecture of Computing systems - ARCS 2008: 21st international conference: proceedings

引用

21st international conference on Architecture of Computing systems, ARCS 2008

ISBN: (纸本)3540781528

The proceedings contain 19 papers. The topics discussed include: system level simulation of autonomic SoCs with TAPES;topology-aware replica placement in fault-tolerant embedded networks;design of gate array circuits using evolutionary algorithms;a hardware packet re-sequencer unit for network processors;dynamic reconfiguration of FlexRay schedules for response time reduction in asynchronous fault-tolerant networks;synthesis of multi-dimensional high-speed FIFOs for out-of-order communication;a novel routing architecture for field-programmable gate-arrays;a predictable simultaneous multithreading scheme for hard real-time;soft real-time scheduling on SMT processors with explicit resource allocation;and a hardware/software codesign of a co-processor for real-time hyperelliptic curve cryptography on a Spartan3 FPGA.

关键词： Field programmable gate arrays (FPGA)

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Latency-insensitive hardware/software interfaces 08

Latency-insensitive Hardware/Software interfaces

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6th ACM/IEEE international conference on Formal Methods and Models for Co-Design

作者： Hoover, Greg Brewer, Forrest Gill, Chris Univ Calif Santa Barbara Santa Barbara CA 93106 USA Washington Univ Washington DC 63130 USA

ISBN: (纸本)9781424424177

Modern embedded system designers face challenges of unprecedented scales, creating systems that integrate functionality spanning disparate scientific domains, with increasing computation demands and ever-stricter power requirements. Meeting the constraints of these systems requires practical design flows that reduce development time without sacrificing design efficiency. Novel design description methodologies coupled with automated and semi-automated synthesis paths greatly accelerate the design of modern hardware systems. In the software space, however, synthesis methods are far from producing co-designs with the necessary efficiency. This is particularly evident at the hardware/software boundary, where the tight coupling of low-level firmware routines and hardware protocols require designers to have deep design knowledge in both domains. To address this issue, we propose a latency-insensitive software execution model that allows direct connection to elastic hardware control topologies.

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system on High-speed Underwater Acoustic Communication with Multi-carrier

System on High-speed Underwater Acoustic Communication with ...

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9th international conference on Signal Processing

作者： Yan Zhenhua Huang Jianguo Han Jing Ran Maohua Northwestern Polytech Univ Coll Marine Xian 710072 Shaanxi Peoples R China

ISBN: (纸本)9781424421787

High-speed underwater acoustic communication with multi-carrier is used for real-time transmission with high data rate and low bit error rate, and it plays an important role in AUV. OFDM (orthogonal frequency division multiplexing) is an attractive multi-carrier communication method around the world. According to the requirements of high-speed underwater acoustic communication with multi-carrier, a system is designed for OFDM communication from hardware and software. The multiple processors with 4 ADSP-TS101s makes up of cluster/data flow associated multiprocessing parallel processing structure as the operation kernel. The receiver composed of multi-channel synchronous sample module and the transmitter with FIFO (first in first out) are designed and implemented And the FPGA is used to realize the logical control and data package. The methods of interrupts of DMA (direct memory access) and ha half-full are used to realize data transmission with high speed at background And the signal synthesis method, DDS (direct digital synthesis), is adopted to realize producing OFDM signal in real time. Through the experiments in a lake, the results show that the system had good stability and real-time processing capability, it can complete the OFDM signal transmission and receiving with high speed.

关键词： Underwater acoustics Underwater communication OFDM Signal synthesis Bit error rate hardware Communication system software Parallel processing Kernel Transmitters

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