Cross toolkits (assembler, linker, debugger, simulator, profiler) are widely used for software-hardwarecodesign;an early creation of cross toolkits is an important success factor for industrial embedded systems. At t...
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Cross toolkits (assembler, linker, debugger, simulator, profiler) are widely used for software-hardwarecodesign;an early creation of cross toolkits is an important success factor for industrial embedded systems. At the hardware design stage systems are subject to significant design alterations including changes in the instruction set of target CPUs. This is a challenging issue for early cross toolkit development. In this paper, we present a new Architecture Description Language (ADL) called ISE language and an approach to early cross toolkit development to cope with hardware design changes. The paper introduces the MetaDSP framework that supports ISE-based construction of cross toolkits and gives brief overview of the MetaDSP applications to industrial projects that proves the industrial strength of the presented approach and tools.
SSC-DASH (Server Side C-DASH) has been developed as a web-based HW/SW codesign tool for designing processors. SSC-DASH obtains a processor definition file via web browser and generates a HW (synthesizable Verilog-HDL ...
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ISBN:
(纸本)9781424442331
SSC-DASH (Server Side C-DASH) has been developed as a web-based HW/SW codesign tool for designing processors. SSC-DASH obtains a processor definition file via web browser and generates a HW (synthesizable Verilog-HDL description) and SWDE (software Development Environment) for the generated processor. The SWDE includes ISS (Instruction Set Simulator), assembler, disassembler and compiler. For the verification of the defined processor, processor developers have to download the generated SWDE, every time, even where changes are small. To improve the usability of this system a web-based interface for the generated SWDE is implemented using Ajax. Using Ajax download of the SWDE becomes unnecessary and makes it possible to verify the processor on the server quickly and easily. This greatly improves the usability of the SWDE. In this paper, we describe implementation of web-based ISS using Ajax.
This paper presents a method to control and acquire the conductivity signal of low-voltage capillary electrophoresis microchip based on SOPC and DDS techniques. The soft-core processor with RISC framework, NIOS II, ac...
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ISBN:
(纸本)9780769532875
This paper presents a method to control and acquire the conductivity signal of low-voltage capillary electrophoresis microchip based on SOPC and DDS techniques. The soft-core processor with RISC framework, NIOS II, acts as the core component. Under the control of NIOS II, the electrode ports are movably supplied DC voltage by the 128-channel electrodes address decoding strobe controller, and the moving field is formed to achieve of the different particles separating in the microchannel of low-voltage electrophoresis microchip. The direct digital frequency synthesis (DDS) modeling is built by DSP Builder. The DDS IP core is generated by Quartus II software. To control the dual phase lock-in amplifier by the DDS orthogonal signals sources. The four-electrode capacitively coupled contactless conductivity detector is designed to achieve the conductivity detection of solution. The design of DDS IP core based on DSP Builder, hardware framework and software design of system are mainly introduced in article.
A novel time-varying Doppler frequency synthesizer is presented in this paper Time-varying Doppler frequency synthesis is one of the most critical problems in high dynamic GPS signal simulator The presented frequency ...
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ISBN:
(纸本)9781424421787
A novel time-varying Doppler frequency synthesizer is presented in this paper Time-varying Doppler frequency synthesis is one of the most critical problems in high dynamic GPS signal simulator The presented frequency synthesizer which may be easily implemented by software and hardware in digital domain can accurately control Doppler frequency and its derivatives of generated signals by means of designing inputting controlling words of carrier NCO, so as to accurately simulate received time-varying carrier Doppler frequency arising from high dynamics between satellites and GPS receivers. Experiment results confirm the correctness and validity of the proposed scheme.
Standards developed by various organizations do not facilitate correct interpretation of business processes unless the standards are based on objective criteria of process decomposition and account for an integrative ...
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ISBN:
(纸本)9781934272343
Standards developed by various organizations do not facilitate correct interpretation of business processes unless the standards are based on objective criteria of process decomposition and account for an integrative role of information. Aspiring to contribute to the emerging science of processes, the presented model of business and manufacturing processes is the first step to a formal objective systematic description of processes, and the ergo-transformation processes in particular. This step is vital for embedding some aspects of intelligence into software and hardware.
In the state-of-the-art hardware/software (HW/SW) co-design of embedded systems, there is a lack of sufficient support for architectural specifications across HW/SW boundaries. Such an architectural specification ough...
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A general purpose system and technique is presented for the separation of target program compilation and fitness evaluation from the primary evolutionary computation system. Preliminary results are presented for two b...
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ISBN:
(纸本)9783540858560
A general purpose system and technique is presented for the separation of target program compilation and fitness evaluation from the primary evolutionary computation system. Preliminary results are presented for two broadly different domains: (1) software generated in the C programming language, (2) hardware designs in Verilog, suitable for synthesis. The presented approach frees the developer from implementing and debugging a complex interpreter, and potentially enables the rapid integration of previously unsupported languages, as well as complex methods of fitness evaluation, by leveraging the availability of external tools. It also enables engineers (especially those in industry) to use preferred/approved tools for which source code may not be readily available, or which may be cost or time prohibitive to reimplement. Efficiency gains are also expected, particularly for complex domains where the fitness evaluation is computationally intensive.
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