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Modelsim verification tool in testing cores-based system-on-chips

Modelsim verification tool in testing cores-based system-on-...

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27th IASTED international conference on Modelling, Identification, and Control

作者： Das, Sunil R. Li, Jun Feng Hossain, Altaf Nayak, Amiya R. Petriu, Emil M. Biswas, Satyendra School of Information Technology and Engineering Faculty of Engineering University of Ottawa Ottawa ON K1N 6N5 Canada Department of Computer and Information Science College of Arts and Sciences Troy University Montgomery AL 36103 United States Department of Electrical Engineering and Technology Georgia Southern University Statesboro GA 30460 United States

ISBN: (纸本)9780889867116

The complexity of modern digital circuits has increased enormously particularly due to paradigm shift from system-on-board to designs embracing embedded cores-based system-on-chips (SOCs). The increased complexity has resulted in a huge challenge in setting up their appropriate fault testing environment. Though enormous efforts were directed to rapidly test very large-scale integrated (VLSI) circuit chips with reasonable cost, with advances in technology, new frontiers emerged. This paper aims at developing a method to verify and test circuit architecture under hardware and software codesign environment, targeting specifically embedded cores-based system-on-chips (SOCs). The well-known concept of design-for-testability (DFT) is utilized in the paper based on the use of ModelSim simulation and verification tool to test simulate the entire design. Some partial results on ISCAS 85 combinational benchmark circuit are provided in the paper, besides a comparison of the results with some previous works.

关键词： Design for testability

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Evolvable systems: From Biology to hardware - 8th international conference, ICES 2008, proceedings

Evolvable Systems: From Biology to Hardware - 8th Internatio...

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8th international conference on Evolvable systems: From Biology to hardware, ICES 2008

ISBN: (纸本)3540858563

The proceedings contain 42 papers. The topics discussed include: a comparison of evolvable hardware architectures for classification tasks;hardware acceleration of an immune network inspired evolutionary algorithm for medical diagnosis;a stepwise dimension reduction approach to evolutionary design of relative large combinational logic circuits;evolutionary graph models with dynamic topologies on the Ubichip;a hardware-software design framework for distributed cellular computing;investigating the suitability of FPAAs for evolved hardware spiking neural networks;on evolutionary synthesis of linear transforms in FPGA;proposal for LDPC code design system using multi-objective optimization and FPGA-based emulation;optimized state assignment for FSMs using quantum inspired evolutionary algorithm;and parallel grammatical evolution for circuit optimization.

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proceedings - 6th ACM and IEEE international conference on Formal Methods and Models for Co-Design, MEMOCODE'08

Proceedings - 6th ACM and IEEE International Conference on F...

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6th ACM and IEEE international conference on Formal Methods and Models for Co-Design, MEMOCODE'08

ISBN: (纸本)9781424424177

The proceedings contain 19 papers. The topics discussed include: programming multicores with Kahn process networks;a choice;arithmetic circuits verification without looking for internal equivalences;from data to events: checking properties on the control of a system;vacuity analysis by fault simulation;rule-based approaches for equivalence checking of specC programs;static deadlock detection for the SHIM concurrent language;a comparison of two systemC/TLM semantic for formal verification;latency-insensitive hardware/software interfaces;directed-logical testing for functional verification of microprocessors;estimating the performance of cache replacement policies;and on the deterministic multi-threaded software synthesis for polychronous specifications.

关键词： Concurrency control

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SoC-C: Efficient programming abstractions for heterogeneous multicore systems on chip

SoC-C: Efficient programming abstractions for heterogeneous ...

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Embedded systems Week 2008 - 2008 international conference on Compilers, Architecture and synthesis for Embedded systems, CASES'08

作者： Reid, Alastair D. Flautner, Krisztian Grimley-Evans, Edmund Lin, Yuan ARM Ltd. United Kingdom University of Michigan United States

ISBN: (纸本)9781605584690

The architectures of system-on-chip (SoC) platforms found in high-end consumer devices are getting more and more complex as designers strive to deliver increasingly compute-intensive applications on near-constant energy budgets. Workloads running on these platforms require the exploitation of heterogeneous parallelism and increasingly irregular memory hierarchies. The conventional approach to programming such hardware is very low-level but this yields software which is intimately and inseparably tied to the details of the platform it was originally designed for, limiting the software's portability, and, ultimately, the architectural choices available to designers of future platform generations. The key insight of this paper is that many of the problems experienced in mapping applications onto SoC platforms come not from deciding how to map a program onto the hardware but from the need to restructure the program and the number of interdependencies introduced in the process of implementing those decisions. We tackle this complexity with a set of language extensions which allows the programmer to introduce pipeline parallelism into sequential programs, manage distributed memories, and express the desired mapping of tasks to resources. The compiler takes care of the complex, error-prone details required to implement that mapping. We demonstrate the effectiveness of SoC-C and its compiler with a "software defined radio" example (the PHY layer of a Digital Video Broadcast receiver) achieving a 3.4x speedup on 4 cores. Copyright 2008 ACM.

关键词： system-on-chip

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Towards model-based integration of tools and techniques for embedded control system design, verification, and implementation

Towards model-based integration of tools and techniques for ...

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1st international Workshop on Model Based Architecting and Construction of Embedded systems, ACES-MB 2008 - Held as Part of the 2008 11th international conference on Model Driven Engineering Languages and systems, MoDELS 2008

作者： Porter, Joseph Karsai, Gábor Völgyesi, Péter Nine, Harmon Humke, Peter Hemingway, Graham Thibodeaux, Ryan Sztipanovits, János Institute for Software Integrated Systems Vanderbilt University Nashville TN 37203 United States

While design automation for hardware systems is quite advanced, this is not the case for practical embedded systems. The current state-of-the-art is to use a software modeling environment and integrated development environment for code development and debugging, but these rarely include the sort of automatic synthesis and verification capabilities available in the VLSI domain. We present a model-based integration environment which uses a graphical architecture description language (EsMoL) to pull together control design, code and configuration generation, platform-specific resimulation, and a number of other features useful for taming the heterogeneity inherent in safety-critical embedded control system designs. We describe concepts, elements, and development status for this suite of tools.

关键词： Embedded systems

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Evolving Digital Circuits in an Industry Standard hardware Description Language

Evolving Digital Circuits in an Industry Standard Hardware D...

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7th international conference on Simulated Evolution and Learning

作者： Cullen, Jamie Univ New S Wales Artificial Intelligence Lab Sydney NSW Australia

ISBN: (纸本)9783540896937

Evolutionary Meta Compilation (EMC) is a recent technique that enables unmodified external applications to seamlessly perform target program compilation and fitness evaluation for an Evolutionary Computation system. Grammatical Evolution (GE) is a method for evolving computer programs in an arbitrary programming language using a grammar specified in Backus-Naur Form. This, paper combines these techniques to demonstrate the evolution of both sequential and combinatorial digital circuits in all Industry Standard hardware Description Language (Verilog) using an external hardware synthesis engine and simulator. Over-all results show the successful evolution of core digital circuit components. An extension to GE is also presented to attempt to increase the probability of maintaining all evolved program's semantic integrity after crossover operations are performed. Early results show performance improvements in applying this technique to the majority of the presented test cases. It is suggested that this feature may also be considered for use in the evolution of software programs in C and other languages.

关键词： Digital circuits

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A system platform design of travelling wave dielectrophoresis microchip based on SOPC

A System platform design of travelling wave dielectrophoresi...

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international conference on Computer Science and software Engineering, CSSE 2008

作者： Honghua, Liao Jun, Yu Jun, Wang Jianjun, Chen Yu, Liao Jinqiao, Yi Department of Electronics Science and Technology Huazhong University of Science and Technology Wuhan Hubei Province China School of Information Hubei Institute for Nationalities Enshi Hubei Province China

ISBN: (纸本)9780769533360

This paper presents a control and acquisition platform design method of travelling wave dielectrophoresis microchip based on SOPC technique. The Direct Digital Frequency synthesis (DDS) modeling is built by using the Digital Signal Processing (DSP) development tool of FPGA, DSP Builder. By the controlling of NIOSII, which embedded in the FPGA (Cyclonll EP2C35) of Altera Corp., the four-phase DDS module outputs four channels AC signals with the same magnitude, and their phase of four channels AC signals are 0°, 90°, 180° and 270°, respectively. They supply control signals for the travelling wave ITO electrodes array. The travelling wave dielectrophoresis electric field is created by the four-channel AC signals, it drives biological particles direction moving to achieve different biological particles separating in the microchannel of dielectrophoresis micochip. Adopting the custom I2C module achieves the configuration of 3-Megapixel CMOS image sensor, MT9T001, which achieves the contactless detection of different biological particles. The design of DDS IP core based on DSP Builder, the design of custom I2C module, the hardware framework and software design of control system is mainly introduced in article. The correctness and practicability of design method is testified by simulation results. © 2008 IEEE.

关键词： Integrated circuit design

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HW/SW Auto-Coupling for Fast IP Integration in SoC Designs

HW/SW Auto-Coupling for Fast IP Integration in SoC Designs

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international conference on Embedded software and systems

作者： Yin-Tsung Hwang Jun-Yen Chen Jun-Jieh Chiu Department of Electrical Engineering National Chung Hsing University Taichung Taiwan

ISBN: (纸本)9780769532875

IP intergration in SoC nowadays contains two design aspects, i.e. hardware interface and software driver. The hardware interface supports necessary signal mapping, protocol translation and data buffering so that an IP can adapt to various system architectures. The software driver provides IP access controls from the software domain in the presence of operating system. The automation of both design processes in a coupling manner is addressed in this paper. We first outline the methodology of automatic interface synthesis and elaborate on the topics of signal mapping, protocol conversion and interface template architecture. We next present the framework of a baseline driver generator and detail the generation schemes of basic file operations and other functions and driver settings. Both tools are linked to form a HW/SW auto-coupling design suite, which features minimum user knowledge toward the hardware and OS details in usage. Some design examples on the interface synthesis tool and an JPEG codec HW/SW codesign example on the integrated design suite are provided to prove the effectiveness of the proposed system.

关键词： Driver circuits Protocols hardware IP networks Converters Generators Signal mapping

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A hardware filesystem implementation for high-speed secondary storage

A hardware filesystem implementation for high-speed secondar...

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2008 international conference on Reconfigurable Computing and FPGAs, ReConFig 2008

作者： Mendon, Ashwin A. Sass, Ron Electrical and Computer Engineering Department University of North Carolina Charlotte 9201 University Blvd. Charlotte NC 28223 United States

ISBN: (纸本)9780769534749

Platform FPGAs are capable of hosting entire Linux-based systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. Filesystems, however, are typically implemented in software as part of the operating system. This presents a challenge as some applications are very sensitive to file I/O latency and Platform FPGA processor cores are clocked at relatively slow frequencies. This paper describes a design and implementation of a filesystem in hardware. A hardware implementation offers several features that have potential of improving certain classes of applications. The filesystem implemented is a simplified version of the well-known UNIX filesy stem and specifically designed to handle a relatively low number of very large files. The design synthesizes but lacks a SATA host controller needed to test it. Instead, Modelsim was used to verify the functionality of four basic operations: open, read, write and remove. synthesis results show that the core uses a modest 3% of the slices (and 3 BRAM blocks) of a Xilinx Virtex-4 FX60 device. By using a behavioral model of a SATA disk controller, sequential read bandwidth simulations achieved over 3 Gb/s for block sizes of 512 bytes. Since physical disks are much slower, these results suggest that a hardware filesystem core offers several benefits with little cost and no loss of performance. © 2008 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Simulation of Model Based system Design Using Real Time Windows

Simulation of Model Based System Design Using Real Time Wind...

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12th World Multi-conference on systemics, Cybernetics and Informatics/14th international conference on Information systems Analysis and synthesis

作者： Moin, Lubna Ali, Shahid Uddin, Vali Natl Univ Sci & Technol Pakistan Engn Coll Karachi Pakistan

ISBN: (纸本)9781934272336

Real-time systems are loosely defined as the class of computer systems that interact with the external world in a time frame defined by the external world. It is an environment where a single computer is a host and a target. After creating a model and simulating it with simulink in normal mode we can generate executable codes with real time workshop. Here we have used MATLAB as an application tool which provide us the specialized tool boxes for specific areas. The real time window target communicates with the executable program acting as a control program and interfaces with the hardware device through the I/O port. Here we tried to analyse a magnetic levitation system. The control goal is to suspend a steel sphere by means of a magnetic field counteracting the force of gravity and to be able to apply a controlled disturbance to force the sphere to follow a predetermined trajectory. The control to be applied is the voltage, which is converted into a current via internal circuitry in the controller located in the mechanical unit. The current passes through and an electromagnet which creates a magnetic field in its vicinity. The sphere is placed along the vertical axis of the electromagnet after the control system is started in the software. In this way a approach towards real time workshop is analysed and applied.

关键词： Magnetic levitation PID controller actuator sensor real time MATLAB simulation

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