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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Gädtke, Sascha Traulsen, Claus Von Hanxleden, Reinhard Real-Time and Embedded Systems Group Dept. of Computer Science Christian-Albrechts-Universität zu Kiel Olshausenstr. 40 D-24098 Kiel Germany

ISBN: (纸本)9781595938244

We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The starting point is a system model written in the synchronous language Esterel, which can be mapped to both hardware and software. Our approach performs the partitioning at the source-code level and preserves the original, strictly synchronous semantics. It is thus platform-independent and allows to use standard simulation and synthesis tools. Furthermore, the source-level partitioning approach presented here should be applicable to non-reactive processing platforms as well. However, the challenge is to partition the program without changing its meaning under any circumstances. In particular, signal scopes and inter-partition signal dependencies must be maintained, which rules out a naive top-level partitioning. We have implemented the co-synthesis approach based on the Columbia Esterel Compiler and have validated it on the Kiel Esterel Processor. As the experimental results confirm, this can significantly reduce execution times and energy consumption per reaction, with minimal additional hardware requirements. Copyright 2007 ACM.

关键词： software engineering

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Complex task activation schemes in system level performance analysis

Complex task activation schemes in system level performance ...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Haid, Wolfgang Thiele, Lothar Zurich Switzerland

ISBN: (纸本)9781595938244

The design and analysis of today's complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applying traditional methods like HW/SW cosimulation is getting increasingly difficult. On the other hand, analytic approaches have proven their usefulness and efficiency for system analysis when end-to-end performance figures like delay, throughput and memory consumption are requested. One of the main drawbacks of these methods is the limited set of systems that can be analyzed with high accuracy: Only simple models for task interaction and task semantics can be used. In this paper, we extend existing methods for analyzing heterogeneous multiprocessor systems such that (a) nonpreemptive scheduling policies, (b) complex activation schemes for tasks and (c) conditional behavior of task executions can be modeled and analyzed. We demonstrate the usefulness of the proposed approach in a case study. Copyright 2007 ACM.

关键词： software architecture

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Combined approach to system level performance analysis of embedded systems

Combined approach to system level performance analysis of em...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Künzli, Simon Hamann, Arne Ernst, Rolf Thiele, Lothar Siemens Building Technologies Group Switzerland TU Braunschweig Germany ETH Zürich Switzerland

ISBN: (纸本)9781595938244

Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume certain system architectures and application domains, and are thus tailored to give tight analysis results for specific systems. We consider two different compositional analysis methods. Both methods have their particular strengths for different architectures and applications. In this paper, we aim to enhance the analysis capabilities for these techniques. A method for event model conversion allows us a seamless integration of the two methods. Finally, we present a detailed case study to show the applicability and benefits of the enhanced performance analysis technique. Copyright 2007 ACM.

关键词： Embedded systems

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A codesign prototyping framework for Wireless LAN transceivers with smart antennas

A codesign prototyping framework for Wireless LAN transceive...

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16th international conference on Computer Communications and Networks

作者： Roy, Sebastien Boudreault, Jean-Francois Dupont, Louis

ISBN: (纸本)9781424412501

OFDM Wireless LANs based on the IEEE 802.11 standard are complex systems in themselves. When smart antennas are used in such systems, both the MAC and the PHY layers must be redefined in order to achieve application-specific goals. As a result, the development of such systems can become impressively heavy. A complete development framework is presented here. It makes use of hardware/software codesign in order to implement all required layers to develop a wireless access point. The entire framework is targeted at an FPGA platform, providing full flexibility and processing power for the development of PHY layers.

关键词： field programmable gate arrays logic design integrated circuit design signal design communication system software communication systems programming environments software prototyping

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A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

A framework for rapid system-level exploration, synthesis, a...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Thompson, Mark Nikolov, Hristo Stefanov, Todor Pimentel, Andy D. Erbas, Cagkan Polstra, Simon Deprettere, Ed F. Department of Computer Science University of Amsterdam Netherlands Leiden Embedded Research Center Leiden University Netherlands

ISBN: (纸本)9781595938244

In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology with the (parallelized) application mapped onto it in only a matter of hours. During this traversal, which offers a high degree of automation, guidance is provided by Daedalus' integrated system-level design space exploration environment. We show that Daedalus offers remarkable potentials for quickly experimenting with different MP-SoC architectures and exploring system-level design options during the very early stages of design. Using a case study with a Motion-JPEG encoder application, we illustrate Daedalus' design steps and demonstrate its efficiency. Copyright 2007 ACM.

关键词： Microprocessor chips

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Energy efficient co-scheduling in dynamically reconfigurable systems

Energy efficient co-scheduling in dynamically reconfigurable...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Hsiung, Pao-Ann Lu, Pin-Hsien Liu, Chih-Wen Department of Computer Science and Information Engineering National Chung Cheng University Chiayi 62102 Taiwan

ISBN: (纸本)9781595938244

Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. hardware designs employ low power techniques such as configuration prefetch and reuse. software designs restrain energy usage by dynamically scaling the voltage of processors. However, when these techniques are implemented in a system, they might be conflicting and thus cancel their mutual benefits, which results in high power consumption and low performance. We propose run-time co-scheduling of hardware and software tasks by using the slack time, which is introduced due to reusing hardware task configurations, for dynamically scaling the processor voltage such that preceding software tasks consume lesser power. At the same time, the reuse of hardware task configurations also result in lower power consumption and higher performance due to fewer number of reconfigurations. The combined effects of hardware configuration reuse and software dynamic voltage scaling result in schedules with a lower power consumption and higher performance than that obtained through individual techniques applied to hardware and software separately. We performed extensive experiments whose results show that irrespective of different slack ratios, number of voltage levels, or hardware partitions, the schedules generated by our proposed method are more energy efficient than methods that either do not apply any runtime techniques or only apply hardware configuration prefetch and reuse. Copyright 2007 ACM.

关键词： software design

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Reliable multiprocessor system-on-chip synthesis

Reliable multiprocessor system-on-chip synthesis

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Zhu, Changyun Gu, Zhenyu Dick, Robert P. Shang, Li ECE Department Queen's University Kingston ON K7L 3N6 Canada EECS Department Northwestern University Evanston IL 60208 United States

ISBN: (纸本)9781595938244

This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of communicating tasks, the proposed algorithm determines a processor core allocation, level of system-level and processor-level structural redundancy, assignment of tasks to processors, floorplan, and schedule in order to minimize system failure rate and area while meeting functionality and timing constraints. Changes to the thermal profile resulting from changes in allocation, assignment, scheduling, and floorplan are modeled and optimized during synthesis, as is the impact of thermal profile on temperature-dependent failure mechanisms. The proposed techniques have the potential to substantially increase MPSoC system mean time to failure compared to area-optimized solutions. If power densities are high and the dominant lifetime failure mechanisms are strongly dependent on temperature, our results indicate that thermal and structural redundancy optimization during synthesis have the potential to greatly increase MPSoC lifetime with low area cost. Copyright 2007 ACM.

关键词： Microprocessor chips

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Automating synthesis of asynchronous communication mechanisms

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FUNDAMENTA INFORMATICAE 2007年第1期78卷 75-100页

作者： Gorgonio, Kyller Cortadella, Jordi Xia, Fei Yakovlev, Alex Univ Politecn Cataluna Dept Software Barcelona Spain Newcastle Univ Sch Elect Elect & Comp Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed processes in digital systems. In previous work, systematic ACM synthesis methods have been proposed. In this paper, we advance this work by developing algorithms and software tools which automate most of the ACM synthesis process. Firstly, an interleaving specification is constructed in the form of a state graph, and secondly, a Petri net model of an "ACM-type" is derived using the theory of regions. The method is applied to a number of "standard" writing and reading policies of ACMs with shared memory and unidirectional control variables.

关键词： asynchronous communication mechanisms Petri nets concurrent and distributed systems embedded systems hardware and software codesign protocols synthesis

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HySim: A fast simulation framework for embedded software development

HySim: A fast simulation framework for embedded software dev...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Kraemer, Stefan Gao, Lei Weinstock, Jan Leupers, Rainer Ascheid, Gerd Meyr, Heinrich Institute for Integrated Signal Processing Systems RWTH Aachen University Germany

ISBN: (纸本)9781595938244

Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology, it still suffers from low simulation speed compared to real hardware. Especially for embedded software developers simulation speed close to real time is important in order to efficiently develop complex software. In this paper a novel, retargetable, hybrid simulation framework (HySim) is presented which allows switching between native code execution and ISS-based simulation. To reach a certain state of an application as fast as possible, all platform-independent parts of the application are directly executed on the host, while the platform dependent code executes on the ISS. During the native code execution a performance estimation is conducted. A case study shows that speed-ups ranging from 7x to 72x can be achieved without compromising debugging accuracy. The performance estimation during native code execution shows an average error of 9.5%. Copyright 2007 ACM.

关键词： Program processors

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ESL design and HW/SW co-verification of high-end software defined radio platforms

ESL design and HW/SW co-verification of high-end software de...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Ng, A.C.H. Weijers, J.W. Glassee, M. Schuster, T. Bougard, B. Van Der Perre, L. IMEC Belgium

ISBN: (纸本)9781595938244

Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require handheld platforms to shift from sets of multiple application specific ICs (ASICs) to multi-purpose Multi-Processor system-on-Chip (MPSoC) on which software Defined Radios (SDR) are run. SDR design faces hard real-time processing and data transfer latency constraints. Designing SDR under stringent time-to-market (cost), energy and real-time processing constraints requires the help of advanced Electronic system-Level (ESL) design methodologies. This paper demonstrates an integrated ESL design flow built on advanced ESL tools to design SDR platforms for handhelds. We share the experience from creation of a high-level virtual platform model down to hardware/software (HW/SW) co-verification of a large scale SoC (5 million gates+). Incremental RTL verification based on co-simulation and co-emulation is also presented. Copyright 2007 ACM.

关键词： Computer software

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