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4th international conference on Cybernetics and Information Technologies, systems and Applications/5th Int Conf on Computing, Communications and Control Technologies

作者： Mohamed, Khalid Eltahir Ali, Borhanuddin Mohd. Jamuar, S. S. Khatun, Sabira Ismail, Alyani University Putra Malaysia (UPM) Malaysia MIMOS Berhad Malaysia

ISBN: (纸本)9781934272244

This paper presents overview of the software defined radio concept. Furthermore it describes the design of CDMA digital transmitter for a multi-standard SDR base band platform. The SDR digital transmitter is based on modified methods to generate VHDL models of communication systems that can be used with same hardware. Because these models consist of the unique functions in the specific air interface environment, identified by different standards, for example CDMA and TDMA. The source code has been written as much as possible in Very High Speed Integrated Circuit hardware Description Language (VHDL) program;the Synopsys software has been used for the design synthesis, simulation and FPGA compiler for compiling and downloading the simulation.

关键词： CDMA transmitter VHDL SDR multi standard

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Predictable real-time software synthesis

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REAL-TIME systemS 2007年第3期36卷 159-198页

作者： Huang, Jinfeng Voeten, Jeroen Corporaal, Henk Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands Embedded Syst Inst Eindhoven Netherlands

Formal theories for real-time systems (such as timed process algebra, timed automata and timed petri nets) have gained great success in the modeling of concurrent timing behavior and in the analysis of real-time properties. However, due to the ineliminable timing differences between a model and its realization, synthesizing a software realization from a model in a predictable way is still a challenging research topic. In this article, we tackle this problem by solving a set of sub-problems. The solution is based on the theoretical results for property prediction proposed in Huang et al. (2003, Real-time property preservation in approximations of timed systems. In: proceedings of 1st ACM and IEEE international conference on formal methods and models for codesign. IEEE Computer Society, Los Alamitos, pp 163-171) and Huang (2005, Predictability in real-time system design. PhD thesis, Eindhoven University of Technology, The Netherlands), where quantitative property relations are established between two absolute/relative "close" real-time systems. This theory basically implies that if two systems are "close", they enjoy "similar" properties. These results cannot be directly applied in practice though, because a model and its realization typically have infinitely large absolute and relative timing differences. We show that this infinite time gap can be bridged through a sequence of carefully constructed intermediate time domains. Then the property-prediction results can be applied to any pair of adjacent time domains in the sequence. Consequently, real-time properties of the implementation can be predicted from the model. We propose two parameterized hypotheses to characterize the timing differences in the sequence and to guide a correctness-preserving design process. It is shown that these hypotheses can be incorporated in a concrete tool set. We demonstrate the feasibility of the predictable synthesis approach through the design of a railroad crossing system.

关键词： real-time systems formal methods program synthesis

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hardware acceleration of matrix multiplication on a Xilinx FPGA 07

Hardware acceleration of matrix multiplication on a Xilinx F...

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ACM/IEEE international conference on Formal Methods and Models for Co-Design

作者： Dave, Nirav Fleming, Kermin King, Myron Pellauer, Michael Vijayaraghavan, Muralidaran MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9781424410507

The first MEMOCODE hardware/software co-design contest posed the following problem: optimize matrix-matrix multiplication in such a way that it is split between the FPGA and PowerPC on a Xilinx Virtex IIPro30. In this paper we discuss our solution, which we implemented on a Xilinx XUP development board with 256 MB of DRAM. The design was done by the five authors over a span of approximately 3 weeks, though of the 15 possible man-weeks, about 9 were actually spent working on this problem. All hardware design was done using Blue-spec systemVerilog (BSV), with the exception of an imported Verilog multiplication unit, necessary only due to the limitations of the Xilinx FPGA toolflow optimizations.

关键词： Acceleration Field programmable gate arrays Switches Communication system control Control systems Random access memory Computer science Artificial intelligence hardware design languages Design optimization

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Three-dimensional multiprocessor system-on-chip thermal optimization

Three-dimensional multiprocessor system-on-chip thermal opti...

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CODES+ISSS 2007: 5th international conference on hardware/software codesign and system synthesis

作者： Sun, Chong Shang, Li Dick, Robert P. ECE Department Queen's University Kingston ON K7L 3N6 Canada EECS Department Northwestern University Evanston IL 60208 United States

ISBN: (纸本)9781595938244

3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density of 3D MPSoCs increases with the number of active layers, resulting in high chip temperatures. This can reduce system reliability, reduce performance, and increase cooling cost. Thermal optimization for 3D MPSoCs imposes numerous challenges. It is difficult to manage assignment and scheduling of heterogeneous workloads to maintain thermal safety. In addition, the thermal characteristics of 3D MPSoCs differ from those of 2D MPSoCs because each stacked layer has a different thermal resistance to the ambient and vertically-adjacent processors have strong temperature correlation. We propose a 3D MPSoC thermal optimization algorithm that conducts task assignment, scheduling, and voltage scaling. A power balancing algorithm is initially used to distribute tasks among cores and active layers. Detailed thermal analysis is used to guide a hotspot mitigation algorithm that incrementally reduces the peak MPSoC temperature by appropriately adjusting task execution times and voltage levels. The proposed algorithm considers leakage power consumption and adapts to inter-layer thermal heterogeneity. Performance evaluation on a set of multiprogrammed and multithreaded benchmarks indicates that the proposed techniques can optimize 3DMPSoC power consumption, power profile, and chip peak temperature. Copyright 2007 ACM.

关键词： Multiprocessing systems

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Managing of software design and development

Managing of software design and development

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11th World Multi-conference on systemics, Cybernetics and Informatics/13th international conference on Information systems Analysis and synthesis

作者： DeVolder, Dennis Zadeh, Jeff Western Illinois Univ Dept Comp Sci Macomb IL 61455 USA Virginia State Univ Dept Math & Comp Sci Petersburg VA 23806 USA

ISBN: (纸本)9781934272152

software development is complex, expensive, time consuming, and usually done by groups of people with varying skills and abilities. software must be planned, organized, and controlled by people who are involved in the development process. Today, computer hardware is capable enough that software can be written that will continue to run unmodified as hardware is changed. Computers are no longer new alternatives to other applications. The number of software applications seems endless and continues to grow with every advance in computer hardware, such as sensors, communication devices, storage, etc. We need to design and develop software in a way similar to that by which we build bridges or sewers. What we build must last for generations without total rebuilding. This requires new approaches for planning, organizing, and developing future software. In this paper we discuss the traditional software project management process as well as current approaches.

关键词： Computer hardware

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VT matrix multiply design for MEMOCODE '07 07

VT matrix multiply design for MEMOCODE '07

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ACM/IEEE international conference on Formal Methods and Models for Co-Design

作者： Simpson, Eric Yu, Pengyuan Schaumont, Patrick Ahuja, Sumit Shukla, Sandeep Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24060 USA

ISBN: (纸本)9781424410507

This design presents a system optimized for complex matrix multiplications on the XUP Virtex-H board. Utilizing the GEZEL HWISW co-simulation environment, the resulting system achieves 25x speedup over a standard software only implementation. Further system level optimization (with DMA) results in the same coprocessor being speedup by at least another order of magnitude.

关键词： Coprocessors Design optimization Field programmable gate arrays Computer architecture Algorithm design and analysis Delay Read-write memory Control system synthesis Runtime Concurrent computing

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Introducing energy and area estimation in HW/SW design flow based on transaction level modeling

Introducing energy and area estimation in HW/SW design flow ...

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18th international conference on Microelectronics (ICM 2006)

作者： Cheema, Muhammad Omer Hammami, Omar ENSTA 32 Blvd Victor F-75739 Paris France

ISBN: (纸本)9781424407644

Transaction Level Modeling (TLM) facilitates the system designer in decision making at early phases of electronic product development. Executable specifications obtained from TLM models are used for the exploration of various architectural parameters and configurations possible for a system. However, traditional design flows based on TLM don't take into account the area and energy consumption of the system which are inevitably the most important constraints in modern embedded system designs. Traditionally, area and energy estimation is incorporated in system design at RTL (Register Transfer Level) which comes later in system design cycles and most of the crucial design decisions for the system has already been taken at that stage. In this paper, we propose a methodology to incorporate area and energy estimation in TLM based system modeling. This methodology allows a system designer take system level design decisions in very early stages of system design hence avoiding redesign efforts and performance bottlenecks in advanced stages of a project. Results obtained by applying our methodology on an image processing application show the robustness of our approach.

关键词： hardware/software codesign behavioral synthesis transaction level modeling area and energy estimation

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system design and function decomposition over devices for Intrusion Detection system

System design and function decomposition over devices for In...

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11th World Multi-conference on systemics, Cybernetics and Informatics/13th international conference on Information systems Analysis and synthesis

作者： Fujita, Naoyuki Japan Aerosp Explorat Agcy Chofu Tokyo 1828522 Japan

ISBN: (纸本)9781934272169

The Internet bandwidth is increasing, and unauthorized access in the Internet is increasing. So the number of unauthorized access in the Internet is very huge. In order to detect these unauthorized accesses, Intrusion Detection system (IDS) is developed. "Cracking Analyzer" ("CA") is one of the systems, which is developed as above purpose. Originally "Cracking Analyzer" is software based system which can run on Linux, Solaris and Windows. But software processing is too slow to process all of the traffics which pass at DMZ (DeMilitarized Zone). So "CA" is implemented to hardware based system. In this paper, we will describe one implementation method on IDS. At first, outline of function and system components of "CA" are described(Chaper 2). At main. section(Chapter 4), hardware implementation using "SPARC lite" CPU and "VirtexII" FPGA chips are described.

关键词： IDS IPS SPARC lite FPGA automaton

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Embedded VLSI accelerators for fingerprint signal processing

Embedded VLSI accelerators for fingerprint signal processing

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IEEE international Symposium on Intelligent Signal Processing

作者： Fons, Mariano Fons, Francisco Canto, Enrique Univ Rovira & Virgili Dept Engn Electron Elect & Automat Tarragona Spain

ISBN: (纸本)9781424408290

Personal identification based on biometrics is nowadays an emerging research subject. Several physiological and behavioral human characteristics have been suggested in the last decades as discriminating features to be used in personal recognition. Among them, fingerprint is the most widely used technique due to its high discriminating power. However, matching fingerprints in an automatic way is still a technical challenge. A compromise in the system pet formance exists: accuracy, security, real-time and cost are some of the critical points to face up to The main contribution of this work is focused on the physical implementation of the recognition system. The design of an embedded system developed by means of hardware/software co-design techniques highlights much more advantages than those traditional software-based solutions. The introduction of programmable logic into the system permits the synthesis of application-specific hardware a ccelerators;to speed up those computationally-expensive signal processing tasks. while keeping the rest of less expensive tasks under the control of a general-purpose microprocessor. The selected system architecture and the proper hardware-software partitioning of the application have made possible the development of an automatic fingerprint matcher system featuring real-time performance at an affordable cost, what is not guaranteed when developing the same matching algorithm under a purely-software platform.

关键词： design of embedded systems fpga-based hardware accelerators hardware-software co-design techniques real-time signal processing

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ASAP07 IEEE - 18th international conference Application-Specific systems, Architectures and Processors

ASAP07 IEEE - 18th International Conference Application-Spec...

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IEEE 18th international conference Application-specific systems, Architectures and Processors, ASAP07

ISBN: (纸本)1424410274

The proceedings contain 46 papers. The topics discussed include: adaptive sensing and image processing with a general-purpose pixel-parallel sensor/processor array integrated circuit;asynchronous regional computation capabilities for digital retinas;low power motion detection with low spatial and temporal resolution for CMOS image sensor;global operations in SIMD cellular processor arrays employing functional asynchronism;development of high-resolution digital vision chip based on CFPE architecture;modelling and implementation of a novel SPR biointerface for time-effective detection of sepsis biomarkers;a software component for network based data acquisition and control applications;system design of an integrated measurement electronic subsystem for bacteria detection using an electrode array and MC-1 magnetotactic bacteria;and hardware/software codesign of image processing applications using transaction level modeling.

关键词： Cellular arrays

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