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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1554 条记录，以下是681-690 订阅

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proceedings - MSE 2007: 2007 IEEE international conference on Microelectronic systems Education: Educating systems Designers for the Global Economy and a Secure World

Proceedings - MSE 2007: 2007 IEEE International Conference o...

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MSE 2007: 2007 IEEE international conference on Microelectronic systems Education: Educating systems Designers for the Global Economy and a Secure World

ISBN: (纸本)076952849X

The proceedings contain 79 papers. The topics discussed include: model-based design of embedded systems;reflections on implementing and teaching an advanced undergraduate course in embedded systems;a senior-level course in hardware-software codesign;challenges and innovations in microelectronics education in developing nations;a novel graduate course takes a systematic approach to teaching digital system timing;simulink based real-time laboratory course development;a unified environment for design entry and 3D animation of analog circuits schematics;capstone design project for a ubiquitous sensor network;introducing TCAD tools in a graduate level device physics course;teaching informatics students the secrets of hardware design;and using an FPGA processor core and embedded Linux for sensor design projects.

关键词： Microelectronics

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SUM IP Core Generator for solving task for RKHS series summation

SUM IP Core Generator for solving task for RKHS series summa...

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9th international conference on the Experience of Designing and Application of CAD systems in Microelectronics

作者： Hahanov, Vladimir Chumachenko, Svetlana Melnik, Dmitriy Taran, Alina Kharkov National University of Radio Electronics 61166 Kharkov Lenin Avenue 14 Ukraine

ISBN: (纸本)9789665335870

Program system SUM IP Core Generator - means for verification of models - formulas of series summation in Reproducing Kernel Hilbert Space (RKHS) which allows to carry out input of the description of the model-formula with the help of the GUI-interface is offered;to model models - formulas with the help of software products Mathematica, Sinplify, Modelsim, Riviera, Active HDL;to generate initial files IP-core in languages of the description of equipment VHDL, Verilog, system C;to generate scripts - files for modelling, synthesis, implementation, time modelling;to synthesize tests, parameters, conditions for verification on basis Testbench;to carry out post-synthesis modelling for revealing mistakes in codes.

关键词： Computer hardware description languages

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Bridging gap between simulation and spreadsheet study

Bridging gap between simulation and spreadsheet study

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Antoine Perrin Frank Ghenassia STMicroelectronics Grenoble France

system architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification of hardware and software. This paper focuses on a comprehensive analysis framework providing platform assembly facilities, system analysis tools, enhanced traffic model and systemC TLM IP. This framework has been intensively used to design and analyze complex SOC Interconnect based on STBus protocol such as the one of 71xx families. By hiding the complexity of a simulation and filling the gap towards spreadsheet study and costly On-Chip analysis using traffic model, architects benefit from an easy access to an efficient simulation for performance evaluation.

关键词： system-on-a-chip Analytical models Computer architecture Generators Real time systems Bridges Filling

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HW/SW co-design for Esterel processing

HW/SW co-design for Esterel processing

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sascha Gädtke Claus Traulsen Reinhard von Hanxleden Real-Time and Embedded Systems Group Department of Computer Science Christian-Albrechts-Universität Kiel Kiel Germany

We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The starting point is a system model written in the synchronous language Esterel, which can be mapped to both hardware and software. Our approach performs the partitioning at the source-code level and preserves the original, strictly synchronous semantics. It is thus platform-independent and allows to use standard simulation and synthesis tools. Furthermore, the source-level partitioning approach presented here should be applicable to non-reactive processing platforms as well. However, the challenge is to partition the program without changing its meaning under any circumstances. In particular, signal scopes and interpartition signal dependencies must be maintained, which rules out a naïve top-level partitioning. We have implemented the co-synthesis approach based on the Columbia Esterel Compiler and have validated it on the Kiel Esterel Processor. As the experimental results confirm, this can significantly reduce execution times and energy consumption per reaction, with minimal additional hardware requirements.

关键词： hardware software Registers Benchmark testing Random access memory Semantics Field programmable gate arrays

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Compilation techniques specific for a hardware cryptography-embedded multimedia mobile processor

Compilation techniques specific for a hardware cryptography-...

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11th World Multi-conference on systemics, Cybernetics and Informatics/13th international conference on Information systems Analysis and synthesis

作者： Fukase, Masa-Aki Sato, Tomoaki Graduate School of Science and Technology Hirosaki University Hirosaki 036-8561 Japan Computer and Network Systems Center Hirosaki University Hirosaki 036-8561 Japan

ISBN: (纸本)9781934272268

A single chip VLSI processor is the key technology of ever growing pervasive computing to answer overall demands for mobility, speed, security, etc. Thus, we have so far exploited a hardware cryptography-embedded multimedia mobile processor architecture, HCgorilla. Since HCgorilla integrates a wide range of techniques from architectures and languages to applications, one-sided design approach is not always useful. HCgorilla needs more complicated strategy, hardware/software (H/S) co-design. The software support of HCgorilla is composed of a Java interface and parallelizing compilers. They are installed in servers to reduce the load and increase the performance of HCgorilla-embedded clients. Since compilers are the essence of software's responsibility, we focus in this article on our recent results about the design, specification, and prototyping of parallelizing compilers for HCgorilla. The compilers are composed of the multicore compiler and LIW compiler. They are specified to abstract parallelism from executable serial codes or the Java interface output and output the codes executable in parallel by HCgorilla. The prototyping compilers are written in Java and evaluated in case of arithmetic media codes compared with a hand compiler. Although the evaluation is primitive, it shows the reasonability of the compilers.

关键词： processor hardware cryptography H/S co-design compiler Java

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Combined approach to system level performance analysis of embedded systems

Combined approach to system level performance analysis of em...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Simon Künzli Arne Hamann Rolf Ernst Lothar Thiele Technologies Group Switzerland Technical University of Braunschweig Germany ETH Zürich Switzerland

Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume certain system architectures and application domains, and are thus tailored to give tight analysis results for specific systems. We consider two different compositional analysis methods. Both methods have their particular strengths for different architectures and applications. In this paper, we aim to enhance the analysis capabilities for these techniques. A method for event model conversion allows us a seamless integration of the two methods. Finally, we present a detailed case study to show the applicability and benefits of the enhanced performance analysis technique.

关键词： Analytical models Performance analysis Jitter Approximation methods Computational modeling Timing Embedded systems

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HySim: A fast simulation framework for embedded software development

HySim: A fast simulation framework for embedded software dev...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Stefan Kraemer Lei Gao Jan Weinstock Rainer Leupers Gerd Ascheid Heinrich Meyr Institute for Integrated Signal Processing Systems RWTH Aachen University Germany

Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology, it still suffers from low simulation speed compared to real hardware. Especially for embedded software developers simulation speed close to real time is important in order to efficiently develop complex software. In this paper a novel, retargetable, hybrid simulation framework (HySim) is presented which allows switching between native code execution and ISS-based simulation. To reach a certain state of an application as fast as possible, all platform-independent parts of the application are directly executed on the host, while the platform dependent code executes on the ISS. During the native code execution a performance estimation is conducted. A case study shows that speed-ups ranging from 7× to 72× can be achieved without compromising debugging accuracy. The performance estimation during native code execution shows an average error of 9.5%.

关键词： Instruments Aerospace electronics Switches Estimation Coprocessors software Libraries

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Ensuring secure program execution in multiprocessor embedded systems: A case study

Ensuring secure program execution in multiprocessor embedded...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Krutartha Patel Sri Parameswaran Seng Lin Shee School of Computer Science and Engineering University of New South Wales Sydney Australia

Multiprocessor SoCs are increasingly deployed in embedded systems with little or no security features built in. Code Injection attacks are one of the most commonly encountered security threats. Most solutions to this problem in the single processor domain are purely software based and have high overheads. A few hardware solutions have been provided for the single processor case, which significantly reduce overheads. In this paper, for the first time, we propose a methodology addressing code injection attacks in a multiprocessor domain. A dedicated security (monitor) processor is used to oversee the application at runtime. Each processor communicates with the monitor processor through a FIFO queue, and is continuously checked. Static analysis of program map and timing profile are used to obtain program information at compile time, which is utilized by the monitor processor at runtime. This information is encrypted using a secure key and stored in the monitor processor. A copy of this secure key is built into the processor's hardware and is used for decryption by the monitor processor. Each basic block of the program is also instrumented with security information that uniquely identifies itself at runtime. The information from static analysis thus allows the monitor processor to supervise the proceedings on each processor at runtime. Our approach uses a combination of hardware and software techniques to keep overheads to a minimum. We implemented our methodology on a commercial extensible processor (Xtensa LX). Our approach successfully detects the execution of injected code when tested on a JPEG multiprocessor benchmark. The results show a small increase of 6.6% in application processors' runtime (clock cycle count) and 35.2% in code size for the JPEG encoder benchmark.

关键词： Security Runtime Monitoring hardware Benchmark testing Transform coding software

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Implementing digital audio effects using a hardware/software co-design approach

Implementing digital audio effects using a hardware/software...

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10th international conference on Digital Audio Effects, DAFx 2007

作者： Pfaff, Markus Malzner, David Seifert, Johannes Traxler, Johannes Weber, Horst Wiendl, Gerhard FH-OÖ/Hagenberg Dept. HSSE Softwarepark 11 A-4232 Hagenberg Austria

ISBN: (纸本)9788890147913

Digital realtime audio effects as of today are realized in software in almost all cases. The hardware platforms used for this purpose reach from multi purpose processors like the Intel Pentium class over embedded processors (e.g. the ARM family) to specialized DSP. The upcoming technology of complete systems on a single programmable chip contrasts such a software centric solution, because it combines software and hardware via some co-design methodology and makes for a promising alternative for the future of realtime audio. Such systems are able to combine the vast amount of computing power provided by dedicated hardware with the flexibility offered by software in a way the designer is free to influence. While the main realization vehicles for these systems - FPGAs - were already promising but unfortunately offered limited possibilities a decade ago [1] they have made rapid progress over the years being one of the product classes that drive the silicon technology of tomorrow. We describe an example for such a realtime digital effects system which was developed using a hardware/software co-design method. While digital realtime audio processing takes place in low latency dedicated hardware units the control and routing of audio streams is done by software running on a 32 bit NIOS II softcore processor. Implementation of the hardware units is done using a DSP centric methodology for raising the abstraction level of VHDL descriptions while still making use of standard of the shelf FPGA synthesis tools. The physical implementation of the complete system uses a rapid prototyping board tailored for communications and audio applications based on an Altera Cyclone II FPGA.

关键词： Field programmable gate arrays (FPGA)

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Pointer re-coding for creating definitive MPSoC models

Pointer re-coding for creating definitive MPSoC models

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Pramod Chandraiah Rainer Dömer Center of Embedded Computer Systems University of California Irvine USA

Today's MPSoC synthesis and exploration design flows start from an abstract input specification model captured in a system level design language. Usually this model is created from a C reference code by encapsulating the computation and the communication using behaviors and channels. However, often pointers in the reference code hamper the necessary analysis and transformations. In this paper, we present an automated approach to re-code and eliminate pointers. By re-coding the pointer accesses to the actual variables, MPSoC models with definitive computational blocks that communicate using explicit channels become possible. Our pointer re-coding approach not only increases synthesizeabil-ity, analyzeability and verifiability by system tools, but also helps the designer in program comprehension. Our experiments show that this approach is not only feasible, but also effective in creating better models of real-life applications in shorter time.

关键词： Arrays Algorithm design and analysis Indexes Computational modeling Encoding Syntactics system-on-a-chip

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