Nowadays, docents are the main force for inheriting and displaying human cultural heritage. However, the experience of visitors largely depends on their knowledge depth and updates. Large language models (LLMs) have d...
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In the field of IoT, RISC-V as an open-source instruction set shows great application potential. On the one hand, this is due to the low cost brought by the hardware open source trend. On the other hand, the modular i...
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The design space of current quantum computers is expansive, with no obvious winning solution, leaving practitioners with a crucial question: “What is the optimal system configuration to run an algorithm?” This paper...
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ISBN:
(数字)9798331541378
ISBN:
(纸本)9798331541385
The design space of current quantum computers is expansive, with no obvious winning solution, leaving practitioners with a crucial question: “What is the optimal system configuration to run an algorithm?” This paper explores hardware design trade-offs across NISQ systems to better guide algorithm and hardware development. Algorithmic workloads and fidelity models drive the evaluation to appropriately capture architectural features such as gate expressivity, fidelity, and crosstalk. As a result of our analysis, we extend the criteria for gate design and selection from only maximizing average fidelity to a more comprehensive approach that additionally considers expressivity with respect to algorithm structures. A custom synthesis-driven compilation workflow that produces minimal circuit representations for a given system configuration drives our methodology and allows us to analyze any gate set effectively. In this work, we focus on native entangling gates (CNOT, ECR, CZ, ZZ, XX, Sycamore, √iSWAP), proposed gates (B Gate,
4
√CNOT, -
8
√CNOT), as well as parameterized gates (FSim, XY). By providing a method to evaluate the suitability of algorithms for hardware platforms, this work emphasizes the importance of hardware-softwarecodesign for quantum computing.
The task of verifying microelectronic hardware designs is as crucial to the design process as it is tedious. Despite numerous helpful methodologies like constraint random testing, it takes an experienced engineer to f...
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Embedded systems in exoskeletons and wearable rehabilitation devices require efficient monitoring of human gait with stringent demands for real-time and reliable performance. Gait trajectory prediction enables full-pr...
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ISBN:
(纸本)9798400702891
Embedded systems in exoskeletons and wearable rehabilitation devices require efficient monitoring of human gait with stringent demands for real-time and reliable performance. Gait trajectory prediction enables full-process perception of future gait patterns. The template matching approach is a promising algorithm for gait trajectory prediction. However, it has challenges in terms of template selection and dynamic stability. We developed DTW-KM Template Selection Method using the DTW distance matrix and K-means to find trajectories with generality and diversity as candidate templates. In addition, we use a matching method combining soft constraints and quadratic weighting, named ScW Template Matching Method. it can balance timeliness, stability and flexibility, and suppress gait phase and trajectory oscillations. Preliminary experimental results show that our method achieves stable prediction of 0.5--1s gait using efficient inference on embedded devices.
Within the DFG funded, archaeology-focused project Collaborative Research Center 1266 (Scales of Transformation) an information system is implemented including roles, processes, hardware and software infrastructure wi...
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Most of the current aerial images of UAVs are stitched together with the help of image post-processing software on the PC side, which has certain inconvenience. Based on the Android platform, the aerial images are tra...
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Side-Channel Attacks (SCAs), which are always considered a severe threat to the security of the cryptographic circuits, today can also be employed to extract IP secrets and neural network models. Hence, developing nov...
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ISBN:
(纸本)9798400702891
Side-Channel Attacks (SCAs), which are always considered a severe threat to the security of the cryptographic circuits, today can also be employed to extract IP secrets and neural network models. Hence, developing novel security solutions at different design levels is crucial. In this paper, we explore recent countermeasures at the circuit, algorithmic, and microarchitecture levels. First, we explain how Reconfigurable Field-Effect Transistor (RFET), as a beyond CMOS technology, enables us to provide both IP and data protection against SCAs at the circuit level. Second, we investigate an automated method for generating masked circuits as an algorithmic solution, and then we review machine learning-based SCA detection mechanisms at the microarchitecture level. Finally, we discuss emerging threats of SCAs from the industrial point of view.
Swarms of autonomous devices are increasing in ubiquity and size, making the need for rethinking their hardware-softwaresystem stack critical. We present HiveMind, the first swarm coordination platform that enables p...
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ISBN:
(纸本)9781450386104
Swarms of autonomous devices are increasing in ubiquity and size, making the need for rethinking their hardware-softwaresystem stack critical. We present HiveMind, the first swarm coordination platform that enables programmable execution of complex task workflows between cloud and edge resources in a performant and scalable manner. HiveMind is a software-hardware platform that includes a domain-specific language to simplify programmability of cloud-edge applications, a program synthesis tool to automatically explore task placement strategies, a centralized controller that leverages serverless computing to elastically scale cloud resources, and a reconfigurable hardware acceleration fabric for network and remote memory accesses. We design and build the full end-to-end HiveMind system on two real edge swarms comprised of drones and robotic cars. We quantify the opportunities and challenges serverless introduces to edge applications, as well as the trade-offs between centralized and distributed coordination. We show that HiveMind achieves significantly better performance predictability and battery efficiency compared to existing centralized and decentralized platforms, while also incurring lower network traffic. Using both real systems and a validated simulator we show that HiveMind can scale to thousands of edge devices without sacrificing performance or efficiency, demonstrating that centralized platforms can be both scalable and performant.
The proceedings contain 56 papers. The topics discussed include: weak inversion model of an inverting CMOS Schmitt trigger;failure number prediction and replacement strategies for electricity meters in service;compens...
ISBN:
(纸本)9781665469890
The proceedings contain 56 papers. The topics discussed include: weak inversion model of an inverting CMOS Schmitt trigger;failure number prediction and replacement strategies for electricity meters in service;compensation method of dc-link current integral deviation for sensorless control of three-phase BLDC motor;arithmetic field circuit complexity bounds for erasure encoders;an energy-efficient processing element design for coarse-grained reconfigurable architecture on FPGA;hardware-software co-design of efficient light-weight self-attention neural network for lithium-ion batteries state-of-charge estimation;a 0.5 V inverter-based analog output-capacitorless low-dropout regulator with bulk-driven transient-enhancing paths;vacuum control measurement system for mass spectrometer;and hardware reusability optimization for high-level synthesis of component-based processors.
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