检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,499 篇 会议
55 篇 期刊文献

馆藏范围

1,554 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

799 篇 工学
- 738 篇 计算机科学与技术...
- 560 篇 软件工程
- 153 篇 电气工程
- 135 篇 电子科学与技术（可...
- 103 篇 信息与通信工程
- 74 篇 控制科学与工程
- 22 篇 机械工程
- 13 篇 动力工程及工程热...
- 11 篇 光学工程
- 10 篇 建筑学
- 9 篇 仪器科学与技术
- 9 篇 生物工程
- 8 篇 材料科学与工程（可...
- 8 篇 土木工程
- 8 篇 生物医学工程（可授...
- 7 篇 安全科学与工程
- 6 篇 航空宇航科学与技...
179 篇 理学
- 104 篇 数学
- 48 篇 系统科学
- 39 篇 物理学
- 16 篇 统计学（可授理学、...
- 9 篇 生物学
- 6 篇 化学
108 篇 管理学
- 89 篇 管理科学与工程(可...
- 29 篇 工商管理
- 23 篇 图书情报与档案管...
15 篇 法学
- 11 篇 社会学
5 篇 经济学
- 5 篇 应用经济学
5 篇 教育学
- 5 篇 教育学
5 篇 医学
- 5 篇 临床医学
4 篇 艺术学
1 篇 农学

主题

359 篇 hardware
177 篇 computer archite...
162 篇 embedded system
135 篇 application soft...
87 篇 field programmab...
83 篇 embedded systems
75 篇 control system s...
69 篇 costs
67 篇 high level synth...
65 篇 computational mo...
65 篇 algorithm design...
64 篇 system-on-a-chip
63 篇 permission
63 篇 embedded softwar...
61 篇 real time system...
52 篇 timing
50 篇 system-on-chip
48 篇 computer science
47 篇 energy consumpti...
46 篇 space exploratio...

机构

10 篇 department of el...
8 篇 univ calif river...
8 篇 center for embed...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 department of co...
5 篇 princeton univ d...
5 篇 school of inform...
5 篇 department of co...
5 篇 philips research...
5 篇 institute for in...
5 篇 technische unive...
4 篇 department of el...
4 篇 ibm thomas j. wa...
4 篇 imec leuven
4 篇 politecn torino ...
4 篇 university of er...
4 篇 tu braunschweig
4 篇 university of do...

作者

9 篇 sri parameswaran
9 篇 ogras umit y.
9 篇 parameswaran sri
9 篇 nikil dutt
7 篇 rolf ernst
7 篇 dick robert p.
7 篇 dutt nikil
7 篇 robert p. dick
7 篇 leupers rainer
7 篇 vahid f
6 篇 jiang wei
6 篇 greg stitt
6 篇 teich juergen
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
6 篇 a. sangiovanni-v...
6 篇 r. ernst
6 篇 jha niraj k.
5 篇 sungjoo yoo

语言

1,535 篇 英文
17 篇 其他
2 篇 中文

检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

共 1554 条记录，以下是701-710 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Complex task activation schemes in system level performance analysis

Complex task activation schemes in system level performance ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Wolfgang Haid Lothar Thiele Computer Engineering and Networks Laboratory Swiss Federal Institute of Technology Zurich Switzerland

The design and analysis of today's complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applying traditional methods like HW/SW co-simulation is getting increasingly difficult. On the other hand, analytic approaches have proven their usefulness and efficiency for system analysis when end-to-end performance figures like delay, throughput and memory consumption are requested. One of the main drawbacks of these methods is the limited set of systems that can be analyzed with high accuracy: Only simple models for task interaction and task semantics can be used. In this paper, we extend existing methods for analyzing heterogeneous multiprocessor systems such that (a) non-preemptive scheduling policies, (b) complex activation schemes for tasks and (c) conditional behavior of task executions can be modeled and analyzed. We demonstrate the usefulness of the proposed approach in a case study.

关键词： Analytical models Delay Decoding Performance analysis Processor scheduling Embedded systems Algorithm design and analysis

来源：评论

学校读者我要写书评

暂无评论

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC

Simultaneous synthesis of buses, data mapping and memory all...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Brett H. Meyer Donald E. Thomas Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the target applications, these systems will also have custom memory and bus architectures. Because of performance and cost constraints, these systems must be carefully designed to balance system partitioning and resource sharing. The sheer size of the design space requires that tools be able to do this balancing. We have developed an augmented simulated annealing synthesis tool that uses system performance and layout evaluation to drive simultaneous data mapping, memory allocation and bus synthesis. Performing these optimizations at the same time, our tool is able to explore a larger design space and take advantage of cost-saving resource sharing unavailable to previous approaches that allocate memories before synthesizing buses. This results in 20% cost reduction for high-performance designs as well as 27% for low-cost designs in comparison with an approach that performs memory allocation and data mapping separately from bus synthesis.

关键词： Resource management Annealing Topology Wire Libraries Limiting Space exploration

来源：评论

学校读者我要写书评

暂无评论

synthesis automatic test system that realizes based on configuration test technology

Synthesis automatic test system that realizes based on confi...

引用

8th international conference on Electronic Measurement and Instruments

作者： Li Yongke Bian Yongqing Department of Optical and Electronic Engineering Ordnance Engineering College China Hebei University of Economics and Business Shijiazhuang China

ISBN: (纸本)9781424411351

The configuration thought of industrial control automation field had been led into, Configuration Art is applied to test field. A configuration test pattern of equipment is put forward according to the multiform requirement of UAV (Unmanned Aerial Vehicle) equipment test. With the various form bus instrument, the test hardware platform of the mix-bus have been founded;Based on the method of Hierarchical Intelligent Control, have solved the automatically generation problem of test process, so, a configuration test software of UAV equipment have been developed. Under this comprehensive testing system, the need of test system can be founded with graph form, through freely disposition test resource;have completed the comprehensive detection of the UAV. Then the narrow application surface and worse adaptability of the normally test system have been surmounted.

关键词： automated test configuration test UAV hierarchical intelligent control

来源：评论

学校读者我要写书评

暂无评论

Thread warping: A framework for dynamic synthesis of thread accelerators

Thread warping: A framework for dynamic synthesis of thread ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Greg Stitt Frank Vahid Department of Electrical and Computer Engineering University of Florida USA Department of Computer Science and Engineering University of California Riverside USA Center of Embedded Computer Systems University of California Irvine USA

We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding up individual threads and by allowing more threads to execute concurrently. Furthermore, thread warping maintains the important separation of function from architecture, enabling portability of applications to architectures with different quantities of microprocessors and FPGA-an advantage not shared by static compilation/synthesis approaches. We introduce a framework of architecture, CAD tools, and operating system that together support thread warping. We summarize experiments on an extensive architectural simulation framework we developed, showing application speedups of 4× to 502×, averaging 130× compared to a multiprocessor system having four ARM11 microprocessors, for eight benchmark applications. Even compared to a 64-processor system, thread warping achieves 11× speedup.

关键词： Instruction sets Field programmable gate arrays Design automation Synchronization Microprocessors system-on-a-chip

来源：评论

学校读者我要写书评

暂无评论

Redefine: Architecture of a SOC fabric for runtime composition of computation structures

Redefine: Architecture of a SOC fabric for runtime compositi...

引用

17th international conference on Field Programmable Logic and Applications

作者： Satrawala, A. N. Varadarajan, Keshavan Alle, Mythri Nandy, S. K. Narayan, Ranjani Indian Inst Sci Bangalore 560012 Karnataka India Morphing Machines Bangalore Karnataka India

ISBN: (纸本)9781424410590

In this paper we propose the architecture of a SoC fabric onto which applications described in a HLL are synthesized The fabric is a homogeneous layout of computation, storage and communication resources on silicon. Through a process of composition of resources (as opposed to decomposition of applications), application specific computational structures are defined on the fabric at runtime to realize different modules of the applications in hardware. Applications synthesized on this fabric offers performance comparable to ASICs while retaining the programmability of processing cores. We outline the application synthesis methodology through examples, and compare our results with software implementations on traditional platforms with unbounded resources.

关键词： system-on-chip

来源：评论

学校读者我要写书评

暂无评论

IFIP TC10 Working conference on international Embedded systems Symposium, IESS 2007

IFIP TC10 Working Conference on International Embedded Syste...

引用

IFIP TC10 Working conference on international Embedded systems Symposium, IESS 2007

ISBN: (纸本)9780387722573

The proceedings contain 42 papers. The special focus in this conference is on Embedded systems. The topics include: Requirements and concepts for transaction level assertion refinement;using a runtime measurement device with measurement-based WCET analysis;implementing real-time algorithms by using the AAA prototyping methodology;run-time efficient feasibility analysis of uni-processor systems with static priorities;approach for a formal verification of a bit-serial pipelined architecture;automotive system optimization using sensitivity analysis;towards a dynamically reconfigurable automotive control system architecture;towards dynamic load balancing for distributed embedded automotive systems;automatic data path generation from C code for custom processors;Interconnect-aware pipeline synthesis for array based reconfigurable architectures;a hybrid approach for system-level design evaluation;constrained and unconstrained hardware-software partitioning using particle swarm optimization technique;power optimization for embedded system idle time in the presence of periodic interrupt services;reducing the code size of retimed software loops under timing and resource constraints;identification and removal of program slice criteria for code size reduction in embedded systems;embedded software development in a system-level design flow;data reuse driven memory and network-on-chip co-synthesis;hardware implementation of the time-triggered Ethernet controller;error containment in the time-triggered system-on-a-chip architecture;generic architecture designed for biomedical embedded systems;utilizing reconfigurable hardware to optimize workflows in networked nodes;configurable medium access control for wireless sensor networks;modelling of software-hardware complexes;Enhancing a real-time distributed computing component model through cross-fertilization;embedded SW design space exploration and automation using UML-based tools and medical embedded systems.

关键词：

来源：评论

学校读者我要写书评

暂无评论

A data protection unit for NoC-based architectures

A data protection unit for NoC-based architectures

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Leandro Fiorin Gianluca Palermo Slobodan Lukovic Cristina Silvano ALaRI-Faculty of Informatics University of Lugano Lugano Switzerland Dipartimento di Elettronica e Informazione Politecnico di Milano Milan Italy

Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights (none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.

关键词： Computer architecture Nickel Random access memory Permission Computer aided manufacturing system-on-a-chip

来源：评论

学校读者我要写书评

暂无评论

Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

Dynamic security domain scaling on symmetric multiprocessors...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Hiroaki Inoue Akihisa Ikeno Tsuyoshi Abe Junji Sakai Masato Edahiro Nihon Denki Kabushiki Kaisha Minato-ku Tokyo JP NEC Informatec Systems Ltd. Kawasaki Kanagawa Japan NEC Corporation System IP Core Research Laboratories Sagamihara Kanagawa Japan

We propose a method for dynamic security domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security domain in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: 1) self-transition management and 2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security domains. The increase in binary code size is less than 40 KB, and the time required for individual state transitions is of a single-millisecond order. This scaling is the first in the world to make possible dynamic changing of the number of processors within a security domain on an ARM SMP.

关键词： Security Context Registers Embedded systems Switches Process control

来源：评论

学校读者我要写书评

暂无评论

A code-generator generator for Multi-Output Instructions

A code-generator generator for Multi-Output Instructions

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Hanno Scharwaechter Rainer Leupers Gerd Ascheid Heinrich Meyr Jonghee M. Youn Yunheung Paek Integrated Signal Processing Systems RWTH Aachen University Germany Software Optimization & Restructuring Research Group Seoul National University South Korea

We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very common in the area of Application Specific Instruction Set Processors (ASIPs) and Digital Signal Processors (DSPs) which are frequently used in system-on-Chips as programmable cores. In order to provide high-level programmability, and consequently guarantee widespread acceptance, sophisticated compiler support for these programmable cores is of high importance. Since it is not possible to model MultiOutput Instructions as trees in the compiler's Intermediate Representation (IR), traditional approaches for code selection are not sufficient. Extending traditional code-generation approaches for MOI-selection is essentially a graph covering problem, which is known to be NP-complete. We present a new heuristic algorithm incorporated in a retargetable code-generator generator capable of exploiting arbitrary inherently parallel MOIs. We prove the concept by integrating the tool into the LCC compiler which has been targeted towards different Instruction Set Architectures based on the MIPS architecture. Several network applications as well as some DSP benchmarks were compiled and evaluated to obtain results.

关键词： Grammar Program processors Generators Assembly Pattern matching Protocols Encryption

来源：评论

学校读者我要写书评

暂无评论

Temperature-aware processor frequency assignment for MPSoCs using convex optimization

Temperature-aware processor frequency assignment for MPSoCs ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Srinivasan Murali Almir Mutapcic David Atienza Rajesh Gupta Stephen Boyd Giovanni De Micheli LSI EPF Lausanne Switzerland Department of Electrical Engineering University of Stanford USA DACYA Complutense University of Madrid Spain Department of Computer Science and Engineering University of California San Diego USA

The increasing processing capability of Multi-Processor systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to achieve the highest performance system operation that satisfies the temperature and power consumption constraints. The frequency of operation of the different processors and the application workload assignment play a critical role in determining the performance, power consumption and temperature profile of the MPSoC. In this paper, we propose novel convex optimization based methods that solve this important problem of temperature-aware processor frequency assignment, such that the total system performance is maximized and the temperature and power constraints are met. We perform experiments on several realistic SoC benchmarks using a cycle-accurate FPGA-based thermal emulation platform, which show that the systems designed using our methods meet the temperature and power consumption requirements at all time instances, while achieving maximum performance.

关键词： Mathematical model Optimization Power demand Steady-state Time frequency analysis Thermal conductivity system-on-a-chip

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共156页 << < 67 68 69 70 71 72 73 74 75 76 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：