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system-level design for FPGAS

System-level design for FPGAS

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2007 international conference on Field Programmable Logic and Applications, FPL

作者： Dickinson, Mark Altera's European Technology Center

ISBN: (纸本)1424410606

Todays FPGA applications are made up of many different functional elements;hardware blocks, software modules, I/O functions and on-chip interconnect fabrics are four major categories of these elements. I will explore some of the characteristics of these categories in order to provide insight into how the creation, or synthesis, of these functional elements can be automated as much as possible. In particular I will focus on unique benefits and challenges FPGAs present when considering such system design tools. The ideas will be illustrated by examples taken from applications in the networking and the image processing areas. These examples will illustrate progress to date as well as highlighting important areas of focus for future developments. © 2007 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Parallel on-chip ciphers development for the third generation mobile telecommunication system

Parallel on-chip ciphers development for the third generatio...

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3rd IASTED international conference on Advances in Computer Science and Technology, ACST 2007

作者： Damaj, Issam W. Electrical and Computer Engineering Deparment Dhofar University P.O. Box 2509 211 Salalah Oman

ISBN: (纸本)9780889866560

The paper focuses on the synthesis of a highly parallel hardware implementation of the main cipher designed for the third generation mobile communication system. The investigated algorithm is the KASUMI block cipher. Currently, KASUMI is well known to be a strong encryption algorithm. The use of such an algorithm within critical applications, such as mobile communication, requires efficient, highly reliable and correct hardware implementation. We will investigate satisfying such requirements by proposing and adopting a step-wise refinement software engineering approach to develop correct hardware circuits. The method uses a formal functional programming notation for specifying algorithms. The parallel behavior is then obtained through the use of a combination of function decomposition strategies, besides, data and process refinement techniques. The refinements are inspired by the operators of Communicating Sequential Processes (CSP) and map easily to programs in Handel-C (a modern C-based high-level langauge with hardware output). In this paper, we obtain several hardware implementations with different performance characteristics by applying different refinements to the algorithm. The developed designs are compiled and tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of these implementations are included.

关键词： C (programming language)

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A computational reflection mechanism to support platform debugging in systemC

A computational reflection mechanism to support platform deb...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Bruno Albertini Sandro Rigo Guido Araujo Cristiano Araujo Edna Barros Williams Azevedo Institute of Computing State University of Campinas-UNICAMP Campinas Brazil Informatics Center UFPE Recife Brazil

system-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like systemC, appeared as a response to the ever increasing complexity of electronics systems design, where complex SoCs composed of several modules integrated on the same chip have become very common. In this scenario, the exploration and verification of several architecture models early in the design flow has played an important role. This paper proposes a mechanism that relies on computational reflection to enable designers to interact, on the fly, with platform simulation models written in systemC TLM. This allows them to monitor and change signals or even IP internal register values, thus injecting specific stimuli that guide the simulation flow through corner cases during platform debugging, which are usually hard to handle by standard techniques, thus improving functional coverage. The key advantages of our approach are that we do not require code instrumentation from the IP designer, do not need a specialized systemC library, and not even need the IP source code to be able to inspect its contents. The reflection mechanism was implemented using a C++ reflection library and integrated into a platform modeling framework. We evaluate our technique through some platform case studies.

关键词： IP networks Libraries Registers Debugging Dictionaries Clocks hardware

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Predator: A predictable SDRAM memory controller

Predator: A predictable SDRAM memory controller

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Benny Akesson Kees Goossens Markus Ringhofer Technische Universiteit Eindhoven Netherlands NXP Semiconductors Research Delft University of Technnology Netherlands Graz University of Technology Austria

Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAMs, are shared between a multitude of IPs to satisfy these requirements at a low cost per bit. However, SDRAMs have highly variable access times that depend on previous requests. This makes it difficult to accurately and analytically determine latencies and the useful bandwidth at design time, and hence to guarantee that hard real-time requirements are met. The main contribution of this paper is a memory controller design that provides a guaranteed minimum bandwidth and a maximum latency bound to the IPs. This is accomplished using a novel two-step approach to predictable SDRAM sharing. First, we define memory access groups, corresponding to precomputed sequences of SDRAM commands, with known efficiency and latency. Second, a predictable arbiter is used to schedule these groups dynamically at run-time, such that an allocated bandwidth and a maximum latency bound is guaranteed to the IPs. The approach is general and covers all generations of SDRAM. We present a modular implementation of our memory controller that is efficiently integrated into the network interface of a network-on-chip. The area of the implementation is cheap, and scales linearly with the number of IPs. An instance with six ports runs at 200 MHz and requires 0.042 mm 2 in 0.13μm CMOS technology.

关键词： Bandwidth SDRAM Memory management Delay Switches Clocks system-on-a-chip

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Compiling code accelerators for FPGAs

Compiling code accelerators for FPGAs

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Walid A. Najjar Computer Science & Engineering University of California Riverside Riverside CA USA

This tutorial addresses the challenges and opportunities presented by compiled FPGA-based code accelerators. In recent years we have witnessed a fast growth of both size and speed of FPGAs. These had been initially designed and marketed as convenient devices for “glue logic.” Later, they became used as fast prototyping platforms. As their size and speed grew, they have been used for the short time to market they can afford. Lately, their size and speed have made them attractive as code accelerator. While the clock speed achievable on a typical FPGA design is about an order of magnitude lower than that on a typical CPU, their advantage comes from two sources: (1) Large degree of instruction and loop level parallelism. Parallel loops can typically be unrolled by factors ranging in the 100s. (2) Increased efficiency of hardware execution. The streaming of the data through a dedicated circuit eliminates a large number of support operations such as data fetch, address calculations, index management, loop control, etc. The combined higher efficiency and parallelism of hardware execution on FPGAs has been shown to result in speedups ranging from the 10s to the 1,000s over traditional processor on frequently executed code segments. However, the main obstacle to wider acceptance of this technology is programmability. FPGAs are typically programmed using hardware Description Languages (HDLs), which poses two problems: Traditional application developers are typically not HDL designers, and HDLs are not well suited for algorithm implementation. Furthermore, the FPGA is an amorphous mass of logic on which the compiler must create a data-path and schedule the computation. Such a task requires the harnessing of technologies developed for parallelizing compilers as well as those developed for high-level synthesis. The main challenge that faces HLL to HDL translation is the paradigm shift from the stored program model to a value-based, data-driven execution - that is, from temporal

关键词： Field programmable gate arrays hardware design languages Parallel processing hardware Tutorials Computer architecture Clocks

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Polaris: A system-level roadmap for on-chip interconnection networks

Polaris: A system-level roadmap for on-chip interconnection ...

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24th international conference on Computer Design

作者： Soteriou, Vassos Eisley, Noel Wang, Hangsheng Li, Bin Peh, Li-Shiuan Princeton Univ Dept Elect Engn Princeton NJ 08544 USA Freescale Semicond Austin TX 78729 USA

ISBN: (纸本)9780780397064

Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, highwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris(1), a system-level roadmap for on-chip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While the Polaris roadmapping toolchain is extensible so new traffic, network designs, an processes can be added, the current version of the roadmap already incorporates 7,872 NoC design points. Polaris is rapid and iterates over all these NoC architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.

关键词： Network-on-chip

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Channel trees: Reducing latency by sharing time slots in time-multiplexed Networks on Chip

Channel trees: Reducing latency by sharing time slots in tim...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Andreas Hansson Martijn Coenen Kees Goossens Electronic Systems Group Eindhovan University of Technology Eindhoven Netherlands Corporate Research Department NXP Semiconductors Eindhoven Netherlands

Networks on Chip (NoC) have emerged as the design paradigm for scalable system on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or soft real-time (SRT) requirements, are integrated on the same chip. To provide time-related guarantees, NoC resources are reserved, e.g. by non-work-conserving time-division multiplexing (TDM). Traditionally, reservations are made on a per-communication-channel basis, thus providing FRT guarantees to individual channels. For SRT applications, this strategy is overly restrictive, as slack bandwidth is not used to improve performance. In this paper we introduce the concept of channel trees, where time slots are reserved for sets of communication channels. By employing work-conserving arbitration within a tree, we exploit the inherent single-threaded behaviour of the resource at the root of the tree, resulting in a drastic reduction in both average-case latency and TDM-table size. We show how channel trees enable us to halve the latter in a car entertainment SoC, and reduce the average latency by as much as much as 52% in a mobile phone SoC. By applying channel trees to an H264 decoder SoC, we increase processor utilisation by 25%.

关键词： Time division multiplexing system-on-a-chip Bandwidth Nickel Resource management Intellectual property SDRAM

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hardware Estimation and synthesis for a codesign system

Hardware Estimation and Synthesis for a Codesign System

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international conference on Signal Processing, Communication and Networking (ICSCN)

作者： M. Sangeetha J. RajaPaul Perinbam Revathy College of Engineering Department of Electronics and Communication Engineering Anna University Guindy India Department of Electronics and Communication Engineering S. A. Engineering College Chennai India

A software model of hardware estimator is developed. The behavioral description is transformed into an intermediate format called control flow graph (CFG). The graph is partitioned into hardware and software. The unoptimized hardware in intermediate graph is estimated by transforming the graph into matrix format. The partitioned hardware of control flow graph is translated as behavioral network graph. The high level synthesis and logic synthesis are performed using the BNG with simple logical transformation. The final RTL obtained from the conventional synthesis method and BNG method for resource and timing constraint were presented. The cost estimation for the various control construction is being tabulated

关键词： hardware High level synthesis Logic Network synthesis Synthesizers Resource management Flow graphs Timing Delay Costs

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New strategies for system design

New strategies for system design

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2007 international conference on Design and Technology of Integrated systems in Nanoscale Era, DTIS 2007

作者： Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine United States Center for Embedded Computer Systems University of Illinois Urbana-Champaign United States UCI

ISBN: (纸本)1424412781

With complexities of systems-on-Chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a SOC out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure. In order to find the solution, we will look first at the system gap between SW and HW designs and derive requirements for the system design flow that includes software as well as hardware. In order to enable new tools for model generation, simulation, synthesis and verification, the design flow has to be well defined with unique abstraction levels, model semantics and model transformations that correspond to design decisions made by designers. We will introduce the concept of model algebra that supports this approach and can serve as un enabler for the extreme makeover of system design and, consequently, system industry. We will support this concept with hard data and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of billion-transistor systems to the basic principles of design science only. © 2007 IEEE.

关键词： system-on-chip

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Compile-time decided instruction cache locking using worst-case execution paths

Compile-time decided instruction cache locking using worst-c...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Heiko Falk Sascha Plazar Henrik Theiling Computer Science 12 University of Dortmund Dortmund Germany AbsInt Angewandte Informatik GmbH Saarbrucken Germany

Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability is highly undesired for real-time systems. The Worst-Case Execution Time (WCET) of a software running on an embedded processor is one of the most important metrics during real-time system design. The WCET depends to a large extent on the total amount of time spent for memory accesses. In the presence of caches, WCET analysis must always assume a memory access to be a cache miss if it can not be guaranteed that it is a hit. Hence, WCETs for cached systems are imprecise due to the overestimation caused by the caches. Modern caches can be controlled by software. The software can load parts of its code or of its data into the cache and lock the cache afterwards. Cache locking prevents the cache's contents from being flushed by deactivating the replacement. A locked cache is highly predictable and leads to very precise WCET estimates, because the uncertainty caused by the replacement strategy is eliminated completely. This paper presents techniques exploring the lockdown of instruction caches at compile-time to minimize WCETs. In contrast to the current state of the art in the area of cache locking, our techniques explicitly take the worst-case execution path into account during each step of the optimization procedure. This way, we can make sure that always those parts of the code are locked in the I-cache that lead to the highest WCET reduction. The results demonstrate that WCET reductions from 54% up to 73% can be achieved with an acceptable amount of CPU seconds required for the optimization and WCET analyses themselves.

关键词： Benchmark testing Optimization Algorithm design and analysis Context software Transform coding Real time systems

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