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system-level power-performance trade-offs in bus matrix communication architecture synthesis

System-level power-performance trade-offs in bus matrix comm...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Pasricha, Sudeep Park, Young-Hwan Kurdahi, Fadi J. Dutt, Nikil Center for Embedded Computer Systems University of California Irvine CA

ISBN: (纸本)1595933700

system-on-chip communication architectures have a significant impact on the performance and power consumption of modern multi-processor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, power-performance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro-models into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our energy macro-models incur less than 5% average absolute error compared to gate-level models. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibits an approximately 20% variation in power and 40% variation in performance on an industrial networking MPSoC application, demonstrating the utility of our approach. © Copyright 2006 ACM.

关键词： Communication systems

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Are current ESL tools meeting the requirements of advanced embedded systems

Are current ESL tools meeting the requirements of advanced e...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Teich, Jürgen University of Erlangen-Nuremberg Germany

ISBN: (纸本)1595933700

Electronic system Level (ESL) tools are becoming more and more important in order to bridge the well-known productivity design gap. This panel brings together specialists from industry and ESL tool houses to discuss whether current ESL tools available are usable and meeting the requirements of the industry. In particular, we would like to know to what degree currently available tools from major ESL tool houses are used for designing what kind of systems in industry, and for what purpose such as analysis, design space exploration, or synthesis, etc. these tools are currently used. Also, we would like to discuss to what degree existing tools can help in reducing design time, and finally, what the industry sees the most challenging features of tools currently not yet available. On the other side, we would like to know the opinion of the ESL tool houses what they see the most important offerings of ESL tools currently available as well as the most challenging points and problems why ESL hasn't really taken off so far. Could this either be an industry issue, a methodology issue, a design issue or a tool issue. © Copyright 2006 ACM.

关键词： Computer aided software engineering

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Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications

Data reuse driven energy-aware MPSoC co-synthesis of memory ...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Issenin, Ilya Dutt, Nikil University of California Irvine CA 92697

ISBN: (纸本)1595933700

The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP-based co-synthesis technique, a mixed ILP-based traditional two-step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach. © Copyright 2006 ACM.

关键词： Multiprocessing systems

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Generic netlist representation for system and PE level design exploration

Generic netlist representation for system and PE level desig...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Gorjiara, Bita Reshadi, Mehrdad Chandraiah, Pramod Gajski, Daniel Center for Embedded Computer Systems University of California Irvine

ISBN: (纸本)1595933700

Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems require more productive design approaches starting from high-level languages such as C. On the other hand, tight constraints of embedded systems require careful design exploration at system level (coarse grained exploration) and at the processing-element (PE) level (fine grained exploration).In this paper we presented GNR, a formal modeling approach, developed to improve productivity of designing systems and processing elements, the same way that traditional ADLs improved productivity for designing processors. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. Using relatively short GNR description, we explored several designs for implementing an MP3 decoder and achieved 3.25 speedup compared to MicroBlaze processor. We have also developed a web-based interface for our tools, so that users can upload and evaluate new architectures described in GNR. Our toolset and GNR is an intermediate step towards synthesis of TLM to RTL. © Copyright 2006 ACM.

关键词： systems analysis

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Transaction level modeling for hardware architecture exploration with IEEE 802.11n receiver example

Transaction level modeling for hardware architecture explora...

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10th international conference on Communication Technology (ICCT 2006)

作者： Lee, Jin Park, Sin-Chong Informat & Commun Univ Sch Engn 119Munjiro Taejon 305732 South Korea

ISBN: (纸本)9781424408009

This paper gives an overview of a transaction level modeling (TLM) design flow for the hardware architecture exploration with systemC. TLM is widely used for hardware-software codesign, since the objective of TLM is the system exploration in the early stage of the design with fast but accurate simulation with abstracted transaction between modules in system. In this paper, we exploit the concept of TLM for the hardware architecture exploration. systemC description methodology for TLM is described and the hardware architecture exploration of IEEE 802.11n PHY receiver is presented.

关键词： Computer hardware

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Fuzzy decision making in embedded system design

Fuzzy decision making in embedded system design

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Di Nuovo, Alessandro G. Palesi, Maurizio Patti, Davide Ascia, Giuseppe Catania, Vincenzo Dipartimento di Ingegneria Informatica e Delle Telecomunicazioni Università Degli Studi di Catania Catania Italy DIIT Università di Catania

ISBN: (纸本)1595933700

The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multi-objective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Pareto-optimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system. © Copyright 2006 ACM.

关键词： Fuzzy systems

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Creation and utilization of a virtual platform for embedded software optimization: An industrial case study

Creation and utilization of a virtual platform for embedded ...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Hong, Sungpack Yoo, Sungjoo Lee, Sheayun Lee, Sangwoo Nam, Hye Jeong Yoo, Bum-Seok Hwang, Jaehyung Song, Donghyun Kim, Janghwan Kim, Jeongeun Jin, Hoonsang Choi, Kyu-Myung Kong, Jeong-Taek Eo, Sookwan CAE Team System LSI Division Samsung Electronics CO. LTD. Flash Software Group Memory Division Samsung Electronics CO. LTD. Storage Team System LSI Division Samsung Electronics CO. LTD. HDD Development Group Storage Division Samsung Electronics CO. LTD. Software Laboratories Mobile SW Platform Samsung Electronics Co. Ltd.

ISBN: (纸本)1595933700

Virtual platform (ViP), or ESL (Electronic system Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called Hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e.g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.

关键词： Embedded systems

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Multi-processor system design with ESPAM

Multi-processor system design with ESPAM

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Nikolov, Hristo Stefanov, Todor Deprettere, Ed Leiden Institute of Advanced Computer Science Leiden University Netherlands

ISBN: (纸本)1595933700

For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system architectures based on a single processor. Thus, the emerging embedded system-on-Chip platforms are increasingly becoming multiprocessor architectures. As a consequence, two major problems emerge, i.e., how to design and how to program such multiprocessor platforms in a systematic and automated way in order to reduce the design time and to satisfy the performance needs of applications executed on these platforms. Unfortunately, most of the current design methodologies and tools are based on Register Transfer Level (RTL) descriptions, mostly created by hand. Such methodologies are inadequate, because creating RTL descriptions of complex multiprocessor systems is error-prone and time *** an efficient solution to these two problems, in this paper we propose a methodology and techniques implemented in a tool called Espam for automated multiprocessor system design and implementation. Espam moves the design specification from RTL to a higher, so called system level of abstraction. We explain how starting from system level platform, application, and mapping specifications, a multiprocessor platform is synthesized and programmed in a systematic and automated way. Furthermore, we present some results obtained by applying our methodology and Espam tool to automatically generate multiprocessor systems that execute a real-life application, namely a Motion-JPEG encoder. © Copyright 2006 ACM.

关键词： Multiprocessing systems

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SHAPES: A tiled scalable software hardware architecture platform for embedded systems

SHAPES: A tiled scalable software hardware architecture plat...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Paolucci, Pier S. Jerraya, Ahmed A. Leupers, Rainer Thiele, Lothar Vicini, Piero ATMEL Roma INFN INFN Dip. Fisica Univ. Roma Italy TIMA INPG 46 Av. Félix Viallet 38031 Grenoble Cedex France Inst. for Integrated Signal Proc. Syst. Aachen Univ. of Technology Germany Zürich Switzerland INFN C/o Dip. Fisica Univ. Roma la Sapienza P.le Aldo Moro 5 00185 Roma Italy

ISBN: (纸本)1595933700

Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A typical SHAPES tile contains a VLIW floating-point DSP, a RISC, a DNP (Distributed Network Processor), distributed on chip memory, the POT (a set of Peripherals On Tile) plus an interface for DXM (Distributed External Memory). The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbours engineering methodologies is adopted for off-chip networking and maximum system density. The SW challenge is to provide a simple and efficient programming environment for tiled architectures. SHAPES will investigate a layered system software, which does not destroy algorithmic and distribution info provided by the programmer and is fully aware of the HW paradigm. For efficiency and QoS, the system SW manages intra-tile and inter-tile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface. © Copyright 2006 ACM.

关键词： Embedded systems

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Thermal-aware high-level synthesis based on network flow method

Thermal-aware high-level synthesis based on network flow met...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Lim, Pilok Kim, Taewhan School of Electrical Enginnering and Computer Science Seoul National University Seoul Korea Republic of

ISBN: (纸本)1595933700

Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1?C and 11.8?C lower peak temperature on the average, compared to that of the conventional low-power and thermalaware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively. © Copyright 2006 ACM.

关键词： Microprocessor chips

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