检索结果-内蒙古大学图书馆

CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Arora, Divya Raghunathan, Anand Ravi, Srivaths Jha, Niraj K. Dept. of Electrical Engineering Princeton University Princeton NJ 08544 NEC Laboratories America Princeton NJ 08540

ISBN: (纸本)1595933700

The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. A major portion of known security attacks against software systems can be attributed to this shortcoming, including the well-known stack overflow, heap overflow, and format string attacks. Despite their limitations, the flexibility, performance, and ease of use of these languages have made them the choice of most embedded software developers. Researchers have proposed various techniques to enhance programs for memory safety;however, they are all subject to severe performance penalties, making their use impractical in most scenarios. In this paper, we present architectural enhancements to enable efficient, memory-safe execution of software on embedded processors. The key insight behind our approach is to extend embedded processors with hardware that significantly accelerates the execution of the additional computations involved in memory-safe execution. Specifically, we design custom instructions to perform various kinds of memory-safety checks and augment the instruction set of a state-of-the-art extensible processor (Xtensa from Tensilica, Inc.) to implement them. We demonstrate the application of the proposed architectural enhancements using CCured, an existing tool for type-safe retrofitting of C programs. The tool uses a type-inferencing engine that is built around strong type-safety theory and is provably safe. Simulations of memory-safe versions of popular embedded benchmarks on a cycle-accurate simulator modeling a typical embedded system configuration indicate an average performance improvement of 2.3x, and a maximum of 4.6x when using the proposed architecture. These enhancements entail minimal (less than 10%) hardware overhead to the base processor. Our approach is completely automated, and applicable to any C program, making it a promising and practi

关键词： Embedded systems

来源：评论

学校读者我要写书评

暂无评论

hardware cryptography-embedded multimedia mobile system

Hardware cryptography-embedded multimedia mobile system

引用

10th World Multi-conference on systemics, Cybernetics and Informatics/12th international conference on Information systems Analysis and synthesis

作者： Fukase, Masa-aki Akaoka, Ryo Sato, Tomoaki Hirosaki Univ Dept Elect & Informat Syst Engn Hirosaki Aomori 0368561 Japan Hirosaki Univ Comp & Network Syst Ctr Hirosaki Aomori 0368561 Japan

ISBN: (纸本)9789806560680

Security aware multimedia mobility is crucial for the further progress of ubiquitous environment. Java has been promising in view of multimedia mobile features and easy treating, but this lacks simplicity in language processing and platform organization. This has resulted in the saturation of increasing the overall performance of ubiquitous network. On the other hand, user security has been really threatened due to diversified open access to the ubiquitous network, while the diversity from small devices to large machines brings about easy access anytime anywhere. Thus, ever growing ubiquitous community makes overall demands for security, speed, and power consciousness in processing large quantity of multimedia data. The key technology to answer these requirements will be a single VLSI (very large scale integration) chip processor and its software support system, We have exploited the H/S (hardware/software) codesign of a hardware cryptography-embedded multimedia mobile processor and its language processing. The processor named HCgorilla is a devised interpreter type Java CPU (central processing unit) with less power and higher throughput for multimedia cryptographic streaming. The language processing for HCgorilla includes a Java interface and parallelizing compilers. We describe in this article our recent results about the overall system of HCgorilla.

关键词： processor hardware cryptography multimedia mobile Java byte code

来源：评论

学校读者我要写书评

暂无评论

system-level power-performance tradeoffs for reconfigurable computing

System-level power-performance tradeoffs for reconfigurable ...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology hag been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology, and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

关键词： hardware/software (HW/SW) codesign power-performance tradeoffs reconfigurable computing (RC)

来源：评论

学校读者我要写书评

暂无评论

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

Modeling operation and microarchitecture concurrency for com...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Zhu, Xinping Qin, Wei Malik, Sharad Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)1581139373

In multiprocessor-based system-on-chips (SOCs), optimizing the communication architecture is often as important-as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time;at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation-level concurrency maps to the microarchitectural-level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication subsystem through a rigorous modeling approach based on a formal concurrency model, the operation state machine (OSM). Our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multiprocessing-element SOC prototypes. We show that, by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design.

关键词： bus design exploration multiprocessor system on-chip communication architecture (OCA) packet-switching network retargetable simulation simulator synthesis

来源：评论

学校读者我要写书评

暂无评论

Efficient exploration of bus-based system-on-chip architectures

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 681-692页

作者： Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Dept Comp Sci & Engn Codesign & Parallel Proc Lab Seoul 151742 South Korea Samsung Elect Yongin 446711 Gyeonggi South Korea

Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.

关键词： communication architecture design space exploration memory allocation multitask performance estimation

来源：评论

学校读者我要写书评

暂无评论

Using Monte Carlo simulation for assessing software reliability

Using Monte Carlo simulation for assessing software reliabil...

引用

10th World Multi-conference on systemics, Cybernetics and Informatics/12th international conference on Information systems Analysis and synthesis

作者： Carnes, Patrick

ISBN: (纸本)9789806560666

system reliability is a combination of the reliability of the Computer software Configuration Items (CSCIs) of the system as well as the hardware Configuration Items (HCIs) of the system. While hardware reliability decreases over time, software reliability normally improves over time. Therefore, during the later stage of the system lifetime, the software reliability component should have an ever-decreasing adverse impact on system reliability. However, software experiences an almost constant maintenance cycle in which either corrective, adaptive, perfective or enhancement activities occur. Since these activities normally introduce defects into the code, software seldom realizes full reliability growth and thus has more of an adverse impact on system reliability than hardware component. Key words: software development, software reliability, software testing.

关键词： software development software reliability software testing

来源：评论

学校读者我要写书评

暂无评论

Communication Interface Generation For HW/SW Architecture In The STARSoC Environment

<bold>Communication Interface Generation For HW/SW Architect...

引用

3rd IEEE international conference on Reconfigurable Computing and FPGAs

作者： Samahi, Abdelhalim Bourennane, El-Bay Boukhechem, Sami Univ Burgundy CNRS UMR 5158 Lab LE21 BP 47870 F-47870 Dijon France

ISBN: (纸本)1424406897

Mapping the application functionality, to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (synthesis Tool for Adaptive and Reconfigurable system-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we presented our reference platform design proposed and the programming model supported. Secondly, we discussed the communication synthesis flow and we presented our architecture models synthesized. Finally, we presented the experimental results of our methodology and demonstrate the effectiveness of our automatic model generation for SoC through the image processing applications.

关键词： system-on-chip

来源：评论

学校读者我要写书评

暂无评论

Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology

Combining hardware reconfiguration and adaptive computation ...

引用

5th IEEE international conference on Field Programmable Technology

作者： Rana, Vincenzo Santambrogio, Marco D. Memik, Seda Ogrenci Sciuto, Donatella Politecn Milan Dipartimento Elettron Informazionee I-20133 Milan Italy Northwestern Univ Dept EEECS Evanston IL 60208 USA

ISBN: (纸本)9780780397286

In the face of dominant communication overheads and reconfiguration cost of programmable hardware often deployed in SoC environments, a new paradigm is necessary to revisit the partitioning and allocation problems. Our aim is to integrate generalized performance models into codesign to explore the gray area between hardware and software effectively. We propose to use the adaptive computation approach. Adaptivity implies that due to input changes the output of the system is updated only re-evaluating those portions of the program affected by the changes. We study the impact of our model onto a SoC architecture consisting of embedded processors and dynamically reconfigurable hardware. We present an image processing application mapped onto this architecture as a case study.

关键词： Microprocessor chips

来源：评论

学校读者我要写书评

暂无评论

A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH

A unified hardware/software runtime environment for FPGA-bas...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Robert Brodersen Artem Tkachenko Hayden Kwok-Hay So Department of Electrical Engineering and Computer Science University of California Berkeley USA

This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. hardware processes inherit the same level of service from the kernel, such as file system support, as typical UNIX software processes. hardware and software components of a design therefore run as hardware and software processes within BORPH's run-time environment. The familiar and language independent UNIX kernel interface facilitates easy design reuse and rapid application development. Performance of our current implementation and our experience with developing a real-time wireless digital signal processing system based on BORPH will be presented.

关键词： hardware Runtime environment Operating systems Kernel Application software software design Field programmable gate arrays Computer interfaces software standards File systems

来源：评论

学校读者我要写书评

暂无评论

TLM/network design space exploration for networked embedded systems

TLM/network design space exploration for networked embedded ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： D. Quaglia F. Fummi N. Bombieri Dipartimento di Informatica Universitá di Verona Verona Italy

This paper presents a methodology to combine Transaction Level Modeling and system/Network co-simulation for the design of networked embedded systems. As a result, a new design dimension is added to the traditional TLM refinement process to represent network configuration alternatives. Each network configuration can be used both to drive architecture refinement and exploration and to validate the system after each refinement step. A general criterion to map functionalities to system and Network models is presented. As a case study, the proposed methodology is applied to the design of a Voice-over-IP client.

关键词： Space exploration Embedded system Internet telephony Computational modeling Computer simulation Permission Computer networks Computer architecture Mobile handsets Wireless sensor networks

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：