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Streamroller:: automatic synthesis of prescribed throughput accelerator pipelines

Streamroller:: automatic synthesis of prescribed throughput ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Scott Mahlke Kevin Fan Manjunath Kudlur Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. Cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements.

关键词： Throughput Pipelines hardware Kernel Design methodology Cost function Linear accelerators High level synthesis Algorithm design and analysis Embedded computing

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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Scott Mahlke Manjunath Kudlur Hyunchul Park Kevin Fan Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable.

关键词： hardware Acceleration Costs Algorithm design and analysis Application software Decoding Energy efficiency Accelerator architectures Computer architecture Laboratories

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Automatic run-time extraction of communication graphs from multithreaded applications

Automatic run-time extraction of communication graphs from m...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Robert P. Dick Ai-Hsin Liu Electrical Engineering and Computer Science Department Northwestern University Evanston IL USA

Embedded system synthesis, multiprocessor synthesis, and thread assignment policy design all require detailed knowledge of the runtime communication patterns among different threads or processes. Researchers have commonly relied on manual estimation, compile- time analysis, or synthetic benchmarks when developing and evaluating synthesis algorithms and thread assignment policies. In a more ideal world, it would be possible to quickly and easily determine the run-time communication properties of large commercial and academic multithreaded applications. This article describes a fully-automated method of extracting run-time communication graphs from multithreaded applications. The resulting graphs may be used to better understand, design, and synthesize application-specific hardware-software systems. The proposed graph extraction method is implemented as a module within the Simics multiprocessor simulator. It presently supports the analysis of arbitrary multithreaded applications running on the Linux operating system. This software is called CETA. It is freely available for academic and non-profit use.

关键词： Runtime Embedded system Application software Yarn Operating systems Data mining Algorithm design and analysis Computational modeling Computer architecture Linux

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hardware based frequency/voltage control of voltage frequency island systems

Hardware based frequency/voltage control of voltage frequenc...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Diana Marculescu Puru Choudhary Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

The ability to do fine grain power management via local voltage selection has shown much promise via the use of voltage/ frequency islands (VFIs). VFI-based designs combine the advantages of using fine-grain speed and voltage control for reducing energy requirements, while allowing for maintaining performance constraints. We propose a hardware based technique to dynamically change the clock frequencies and potentially voltages of a VFI system driven by the dynamic workload. This technique tries to change the frequency of a synchronous island such that it will have efficient power utilization while satisfying performance constraints. We propose a hardware design that can be used to change the frequencies of various synchronous islands interconnected together by mixed-clock/mixed-voltage FIFO interfaces. Results show up to 65% power savings for the set of benchmarks considered with no loss in throughput.

关键词： Frequency hardware Voltage control Clocks Dynamic voltage scaling Energy management Power system management Power engineering computing Power engineering and energy Throughput

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Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure

Efficient computation of buffer capacities for multi-rate re...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Marco Bekooij Gerard Smit Pierre Jansen Maarten Wiggers University of Twente Enschede Netherlands Philips Research Eindhoven Netherlands

A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buffers in order to control jitter. This requires the derivation of buffer capacities that both satisfy the temporal constraints as well as constraints on the buffer capacity. Existing exact solutions suffer from the computational complexity associated with the required conversion from a multi-rate dataflow graph to a single-rate dataflow graph. In this paper we present an algorithm, with linear computational complexity, that does not require this conversion and that determines close to minimal buffer capacities. The algorithm is applied to an MP3 play-back application that is mapped on our network based multi-processor system.

关键词： Real time systems Throughput Delay Control systems Jitter Computational complexity system-on-a-chip Streaming media Permission Containers

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Resource virtualization in real-time CORBA middleware

Resource virtualization in real-time CORBA middleware

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Christopher D. Gill Department of Computer Science and Engineering Washington University Saint Louis MO USA

Middleware for parallel and distributed systems is designed to virtualize computation and communication resources so that a more abstract and consistent view of those resources is presented to the applications that use them. Providing such a consistent virtualization in distributed real-time and embedded systems becomes increasingly challenging due to application constraints such as timeliness and resource constraints such as CPU speed, power, memory, and bandwidth limitations, which also must be considered. This paper describes several examples of real-time CORBA middleware and examines how different constraints impact the way in which resources are virtualized in each case. Particular attention is paid to which details are hidden from users of the middleware, which details are exposed in the middleware's programming model, and how the hidden and exposed details interact to shape middleware design and implementation choices.

关键词： Resource virtualization Middleware Real time systems Application virtualization Distributed computing Concurrent computing Embedded system Programming profession Application software Computer architecture

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A run-time, feedback-based energy estimation model For embedded devices

A run-time, feedback-based energy estimation model For embed...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chandra Krintz Selim Gurun Department of Computer Science University of California슠Santa Barbara Santa Barbara CA USA

We present an adaptive, feedback-based, energy estimation model for battery-powered embedded devices such as sensor network gate-ways and hand-held computers. Our technique maps hardware and software counters to energy consumption values using a set of first order, linear regression equations. Our system is novel in that it combines online and offline techniques to enable runtime power prediction. Our system employs an offline instantiated model that it continuously updates using feedback from a readily available battery monitor within the device. We empirically evaluate our model and detail its robustness, accuracy, and computational cost. We also analyze the stability of the model in the presence of feedback errors. We demonstrate that our approach can achieve an error rate of 1% (extant techniques: 2.6% to 4%) for computationally bound tasks and 6.6% (extant techniques: 11%) for communication bound tasks.

关键词： Runtime Power system modeling Feedback Computer networks Embedded computing Handheld computers hardware Counting circuits Energy consumption Linear regression

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Automatic selection of application-specific instruction-set extensions

Automatic selection of application-specific instruction-set ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Carlo Galuzzi Elena Moscu Panainte Yana Yankova Koen Bertels Stamatis Vassiliadis Computer Engineering EEMCS Delft University of Technology Delft Netherlands

In this paper, we present a general and an efficient algorithm for automatic selection of new application-specific instructions under hardware resources constraints. The instruction selection is formulated as an ILP problem and efficient solvers can be used for finding the optimal solution. An important feature of our algorithm is that it is not restricted to basic-block level nor does it impose any limitation on the number of the newly added instructions or on the number of the inputs/outputs of these instructions. The presented results show that a significant overall application speedup is achieved even for large kernels (for ADPCM decoder the speedup ranges from times1.2 to times3.7) and that our algorithm compares well with other state-of-art algorithms for automatic instruction set extensions.

关键词： hardware MIMO Clustering algorithms Parallel processing Algorithm design and analysis Computer aided instruction Decoding Kernel Computational complexity Permission

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A methodology for design of application specific deadlock-free routing algorithms for NoC systems

A methodology for design of application specific deadlock-fr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Vincenzo Catania Rickard Holsmark Shashi Kumar Maurizio Palesi Universita degli Studi di Catania Catania Sicilia IT Jönköping University Sweden University of Catania Italy

In this paper, we present a methodology to specialize the routing algorithm in routing table based NoC routers. It tries to maximize the communication performance while ensuring deadlock free routing for an application. We demonstrate through analysis that routing algorithms generated by our methodology have higher adaptiveness as compared to turn-model based deadlock free routing algorithms for a mesh topology NoC architecture. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. The routing algorithms generated by the proposed methodology achieve an improvement in delay close to 50% and 30% over deterministic XY routing algorithm and adaptive odd-even routing algorithm respectively.

关键词： Design methodology Algorithm design and analysis system recovery Routing Network-on-a-chip Network topology Communication networks Telecommunication traffic Communication switching Mesh generation

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Efficient exploration of bus-based system-on-chip architectures

Efficient exploration of bus-based system-on-chip architectu...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Dept Comp Sci & Engn Codesign & Parallel Proc Lab Seoul 151742 South Korea Samsung Elect Yongin 446711 Gyeonggi South Korea

Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.

关键词： communication architecture design space exploration memory allocation multitask performance estimation

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