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The pipeline decomposition tree:: an analysis tool for multiprocessor implementation of image processing applications

The pipeline decomposition tree:: an analysis tool for multi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Shuvra S. Bhattacharyya Dong-Ik Ko Department of Electrical and Computer Engineering Institute for Advanced Computer Studies University of Maryland College Park USA

Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resource-related constraints. As this complexity increases, the application of single-chip multiprocessor technology is attractive. To address the challenges of mapping image processing applications onto embedded multiprocessor platforms, this paper presents a novel data structure called the pipeline decomposition tree (PDT), and an associated scheduling framework, which we refer to as PDT scheduling. PDT scheduling exploits both heterogeneous data parallelism and task-level parallelism, which are important considerations for scheduling image processing applications. This paper develops the PDT representation for system synthesis, and presents methods using the PDT to derive customized pipelined architectures that are streamlined for the given implementation constraints.

关键词： Pipelines Image analysis Image processing Processor scheduling Application software Embedded system Parallel processing Space exploration Multidimensional signal processing Embedded computing

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hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

Hardware assisted pre-emptive control flow checking for embe...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Sri Parameswaran Roshan G. Ragel National ICT Australia University of New South Wales Sydney NSW Australia

Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffer from significant code size penalties, resulting in poor performance. Proposed hardware-assisted approaches are not scalable and therefore cannot be implemented in real embedded systems. This paper presents a scalable, cost effective and novel fault detection technique, to ensure proper control flow of a program. This technique includes architectural changes to the processor and software modifications. While architectural refinement incorporates additional instructions, the software transformation utilizes these instructions into the program flow. Applications from an embedded systems benchmark suite are used for testing and evaluation. The overheads are compared with the state of the art approach that performs the same error coverage using software-only techniques. Our method has greatly reduced overheads compared to the state of the art. Our approach increased code size by between 3.85-11.2% and reduced performance by just 0.24-1.47% for eight different industry standard applications. The additional hardware (gates) overhead in this approach was just 3.59%. In contrast, the state of the art software- only approach required 50-150% additional code, and reduced performance by 53.5-99.5% when error detection was inserted.

关键词： hardware Application software Computer errors Australia software performance Runtime Computer crashes Monitoring Embedded software Embedded system

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Automatic phase detection for stochastic on-chip traffic generation

Automatic phase detection for stochastic on-chip traffic gen...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Tanguy Risset Antoine Fraboulet Antoine Scherrer LIP ENS de Lyon Lyon France CITI-INSA de Lyon Villeurbanne France

(NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently done using traffic generators which emulate the SoC components (IPs) behavior: processors, hardware accelerators, etc. Traffic generated by processor-like IPs is highly non-regular, it must be decomposed into program phases. We propose an original feature for NoC prototyping, inspired by techniques used in processor architecture performance evaluation: the automatic detection of traffic phases. Integrated in our NoC prototyping environment, this feature permits to have a completely automatic toolchain for the generation of stochastic traffic generators. We show that our traffic generators emulate precisely the behavior of processors and that our environment is a versatile tool for networks-on-chip prototyping. Simulations are performed in a systemC-based simulation environment with a mesh network-on-chip (DSPIN) and a processor running MP3 decoding applications.

关键词： Phase detection Stochastic processes Network-on-a-chip Traffic control Telecommunication traffic Prototypes system-on-a-chip hardware Computational modeling Space exploration

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Heterogeneous multiprocessor implementations for JPEG:: a case study

Heterogeneous multiprocessor implementations for JPEG:: a ca...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Andrea Erdos Sri Parameswaran Seng Lin Shee School of Computer Science and Engineering University of New South Wales Sydney Australia NICTA Sydney Australia

Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we explore the use of multiple cores to speed up the JPEG compression algorithm. We show two methods to parallelize this algorithm: one, a master-slave model; and two, a pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues. We show that even with this relatively simple application, parallelization can be carried out with up to nine processors with utilization of between 50% to 80%. We obtained speed ups of up to 4.6X with a seven core system with an area increase of 3. 1X.

关键词： Australia Parallel processing Master-slave Pipelines Intellectual property Power system modeling Multicore processing Computer architecture Multiprocessing systems Instruction sets

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Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations

Yield prediction for architecture exploration in nanometer t...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： T. Grabner F. Catthoor M. Miranda P. Roussel A. Papanikolaou IMEC vzw Leuven Belgium

Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing violations. Conventional yield models do not allow to accurately analyze this, at least not at the system level. In this paper we propose a technique to estimate this system level yield loss for a number of alternative memory organization implementations. This can aid the designer into making educated trade-offs at the architecture level between energy consumption and parametric timing yield by using memories from different available libraries with different energy/performance characteristics considering the impact of manufacturing variations. The accuracy of this technique is very high, an average error of less than 1% is reported, which enables an early exploration of the available options.

关键词： Predictive models Timing Energy consumption Embedded system Performance loss Yield estimation Manufacturing Power system reliability Real time systems system-level design

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Increasing the throughput of an adaptive router in network-on-chip (NoC)

Increasing the throughput of an adaptive router in network-o...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Nader Bagherzadeh Seung Eun Lee Department of Electrical Engineering and Computer Science University of California Irvine CA USA

In this paper, we propose a simple and efficient mechanism to increase the throughput of an adaptive router in network-on-chip (NoC). One of the most serious disadvantages of fully adaptive wormhole routers is its performance degradation due to the routing decision time. The key idea to overcome this shortcoming is the use of different clocks in a head flit and body flits, because the body flits can be forwarded immediately and the FIFO usually operates faster than route decision logic in an adaptive router. The major contributions of this paper are: 1) a proposal of a simple and efficient mechanism to improve the performance of fully adaptive wormhole routers, 2) a quantitative evaluation of the proposed mechanism showing that the proposed one can support higher throughput than a conventional one, and 3) an evaluation of hardware overhead for the proposed router. In summary, the proposed clock boosting mechanism enhances the throughput of the original adaptive router by increasing the accepted load and decreasing the average latency in the region of effective bandwidth.

关键词： Network-on-a-chip Throughput Adaptive systems Clocks Degradation Routing Logic Proposals hardware Boosting

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Battery discharge aware energy feasibility analysis

Battery discharge aware energy feasibility analysis

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Karsten Albers Frank Slomka Henrik Lipskoch University of Oldenburg Germany

It is observed that pulsed discharge currents allow to drain the battery with a higher specific power. Thus they improve the batteries durability and discharge performance. The question is how can the allowed discharge of a battery be modeled. Embedded real-time systems often rely on batteries. For these systems it is necessary to prove both, real-time feasibility and the constraint to not exceed the allowed discharge currents. This paper presents a unified approach for both objectives using the flexible model of event streams, because it allows both to model a complex allowed- discharge curve and the real-time requirements for complex task stimuli. We present the model and the calculation of the allowed and requested discharge curves. Together with the known event- stream based real-time feasibility analysis this allows a unified analysis of both aspects of the system. This work enables the modeling of complex discharge requirements of batteries for real-time systems.

关键词： Batteries Power system modeling Real time systems Power system reliability Embedded system Job shop scheduling Reliability theory Energy consumption Permission Timing

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Bounded arbitration algorithm for QoS-supported on-chip communication

Bounded arbitration algorithm for QoS-supported on-chip comm...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Gereon Weiss Joerg Henkel Mohammad Abdullah Al Faruque Computer Science Department University of Karlsruhe Karlsruhe Germany

Time-critical multi-processor systems require guaranteed services in terms of throughput, bandwidth etc. in order to comply to hard real-time constraints. However, guaranteed-service schemes suffer from low resource utilization. To the best of our knowledge, we are presenting the first approach for on-chip communication that provides a high resource utilization under a transaction-specific, flexible (i.e. different classifications on data exchange) communication scheme. It does provide tight time-related guarantees. Hence, we are presenting our bounded arbitration scheme considering lower and upper bounds for each type of transaction level. We demonstrate its advantages by means of a complete MPEG4 decoder case study and achieve under these constraints a bandwidth utilization of up to 100%, on an average 97% with a guaranteed (100%) bandwidth.

关键词： Quality of service Network-on-a-chip Bandwidth Embedded system system-on-a-chip Time factors Resource management Routing Throughput Real time systems

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A formal approach to robustness maximization of complex heterogeneous embedded systems

A formal approach to robustness maximization of complex hete...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Razvan Racu Rolf Ernst Arne Hamann Institute of Computer and Communication Network Engineering Technical University of Braunschweig Germany

Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variations of properties like execution and transmission delays, input data rates, CPU clock rates, etc., has found less attention despite its practical relevance. In this paper we introduce robustness metrics and propose an algorithm considering these metrics in design space exploration and system optimization. The algorithm can optimize for static and for dynamic robustness, the latter including system or designer reactions to property variations. We explain several applications ranging from platform optimization to critical component identification. By means of extensive experiments we show that design space exploration pursuing classical design goals does not necessarily yield robust systems, and that our method leads to systems with significantly higher design robustness.

关键词： Robustness Embedded system Algorithm design and analysis Space exploration Design optimization Cost function Timing Energy consumption Delay Clocks

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Layout aware design of mesh based NoC architectures

Layout aware design of mesh based NoC architectures

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Karam S. Chatha Krishnan Srinivasan Department of Computer Science and Engineering Arizona State University Tempe AZ USA

Design of system-on-chip (SoC) with regular mesh based network-on-chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates system- level floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC architecture with complete information of the floorplan. In comparison to an existing approach, our technique results in lower total power consumption and much lower link power consumption.

关键词： Network-on-a-chip Energy consumption Computer architecture Mesh generation Routing Bandwidth Topology Computer science Design engineering system-on-a-chip

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