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international conference on hardware/software codesign and system synthesis (CODES)

作者： Todor Stefanov Ed Deprettere Hristo Nikolov Leiden Institute of Advanced Computer Science Leiden University Netherlands

For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system architectures based on a single processor. Thus, the emerging embedded system-on-Chip platforms are increasingly becoming multiprocessor architectures. As a consequence, two major problems emerge, i.e., how to design and how to program such multiprocessor platforms in a systematic and automated way in order to reduce the design time and to satisfy the performance needs of applications executed on these platforms. Unfortunately, most of the current design methodologies and tools are based on Register Transfer Level (RTL) descriptions, mostly created by hand. Such methodologies are inadequate, because creating RTL descriptions of complex multiprocessor systems is error-prone and time consuming. As an efficient solution to these two problems, in this paper we propose a methodology and techniques implemented in a tool called ESPAM for automated multiprocessor system design and implementation. ESPAM moves the design specification from RTL to a higher, so called system level of abstraction. We explain how starting from system level platform, application, and mapping specifications, a multiprocessor platform is synthesized and programmed in a systematic and automated way. Furthermore, we present some results obtained by applying our methodology and ESPAM tool to automatically generate multiprocessor systems that execute a real-life application, namely a Motion-JPEG encoder.

关键词： Unsolicited electronic mail Application software Multiprocessing systems Embedded system Design methodology Design automation Computer networks Computational modeling Computer science system-on-a-chip

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Creation and utilization of a virtual platform for embedded software optimization:: an industrial case study

Creation and utilization of a virtual platform for embedded ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jeong-Taek Kong Bum-Seok Yoo Donghyun Song Hye Jeong Nam Jaehyung Hwang Janghwan Kim Sangwoo Lee SooKwan Eo Sungjoo Yoo Kyu-Myung Choi HoonSang Jin Jeongeun Kim Sheayun Lee Sungpack Hong CAE Team System LSI Division CAE Team System LSI Division Samsung Electronics Company Limited South Korea Flash Software Group Memory Division Samsung Electronics Company Limited South Korea Flash Software Group Memory Division Storage Team System LSI Division Samsung Electronics Company Limited South Korea Storage Team System LSI Division HDD Development Group Storage Division Samsung Electronics CO. LTD South Korea Mobile SW Platform Samsung Electronics CO. LTD South Korea

Virtual platform (ViP), or ESL (electronic system level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e. g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.

关键词： Embedded software Computer industry system-level design Hard disks Timing Accuracy Programming Design optimization Analytical models Performance analysis

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Fuzzy decision making in embedded system design

Fuzzy decision making in embedded system design

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Vincenzo Catania Giuseppe Ascia Maurizio Palesi Davide Patti Alessandro G. Di Nuovo Universita degli Studi di Catania Catania Sicilia IT DIIT Università di Catania Catania Italy Dipartimento di Ingegneria Informatica e delle Telecomunicazioni Università degli Studi di Catania Catania Italy

The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multi- objective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Pareto- optimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system.

关键词： Fuzzy systems Decision making Embedded system Space exploration Application specific processors Computational modeling Computer simulation Computer applications Algorithm design and analysis Design optimization

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A UML for a multiprocessor system-on-chip

A UML for a multiprocessor system-on-chip

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10th World Multi-conference on systemics, Cybernetics and Informatics/12th international conference on Information systems Analysis and synthesis

作者： Bique, Stephen Virginia State Univ Dept Math & Comp Sci Petersburg VA 23806 USA

ISBN: (纸本)9789806560697

A low-level language is the right tool to develop applications for some embedded systems. Notwithstanding, a high-level language provides a proper environment to develop the programming tools. The target device is a system-on-chip consisting of an array of processors with only local communication. Applications include typical streaming applications for digital signal processing. We describe the hardware model and stress the advantages of a flexible device. We introduce IDEA, a graphical integrated development environment for an array. A proper foundation for software development is a UML and standard programming abstractions in object-oriented languages.

关键词： multiprocessor system-on-chip digital signal processing unified modeling language

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Thermal-aware high-level synthesis based on network flow method

Thermal-aware high-level synthesis based on network flow met...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Taewhan Kim Pilok Lim School of Electrical Enginnering and Computer Science Seoul National University Seoul South Korea

Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1degC and 11.8degC lower peak temperature on the average, compared to that of the conventional low-power and thermal- aware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively.

关键词： High level synthesis Capacitance Energy consumption Equations Temperature measurement Iterative algorithms Computer science Computer network reliability Packaging Costs

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Floorplan driven leakage power aware IP-based SoC design space exploration

Floorplan driven leakage power aware IP-based SoC design spa...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Kamal Khouri Fadi Kurdahi Magdy Abadir Nikil Dutt Aseem Gupta Center for Embedded Computer Systems University of California Irvine CA USA Design Technology Organization Freescale Semiconductor Inc. Austin TX USA

Multi-million gate system-on-chip (SoC) designs increasingly rely on intellectual property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway. In IP-based design there has been a disconnect between system level design and physical level steps such as floorplanning which can lead to failures in manufactured chips. This necessitates coupling between system level and physical level design steps. The leakage power of an IP-block increases with its temperature which is dependent on the SoC's floorplan due to thermal diffusion. We have observed that different floorplans of the same SoC can have up to 3X difference in leakage power. Hence the system designer needs to be aware of this design space between floorplans and leakage power. We propose a leakage aware exploration (LAX) framework which enables the system designer to create this design space early in the design cycle and provides an opportunity to make changes in the system design. We show the size of the design space generated by applying LAX on ten industrial SoC designs from Freescale Semiconductor Inc. and observe that the leakage power can vary by as much as 190% for 65% difference in the inactive area.

关键词： Space exploration system-on-a-chip Intellectual property Space technology Energy consumption system-level design Manufacturing Temperature dependence Power generation Aerospace industry

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hardware/software exploration for an anti-collision radar system

Hardware/Software exploration for an anti-collision radar sy...

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49th IEEE international Midwest Symposium on Circuits and systems

作者： Le Beux, S. Gagne, V. Aboulhamid, E. M. Marquet, Ph. Dekeyser, J. -L. Univ Sci & Technol Lille Lab Informat Fondamentale Lille Lille France Univ Montreal Dept Comp Sci & Res Operat Montreal PQ Canada

ISBN: (纸本)9781424401727

Anti-collision radars help prevent car accidents by detecting obstacles in front of vehicles equipped with such systems. This task traditionally relies on a correlator, which searches for similarities between an emitted and a received wave. Other modules can then use the information produced by the correlator to compute the distance and the relative speed between the moving vehicle and the obstacle. We implemented such a system using FPGAs. We used hardware blocks to implement the high demanding computing correlator and a soft-core processor to compute the distances and speeds. In order to improve the maximum detection distance reached by the correlation algorithm, we developed and tested a modified version of a Higher Order Statistics based algorithm. This work results in a detailed description of this new algorithm, its possible implementations and the corresponding FPGA synthesis results.

关键词： Radar systems

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Energy minimization for real-time systems with (m, k)-guarantee

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 717-729页

作者： Niu, Linwei Quan, Gang Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Energy consumption and quality of service (QoS) are two primary concerns in the development of today's pervasive computing systems. While most of the current research in energy-aware real-time scheduling has been focused on hard real-time systems, a large number of practical applications and systems exhibit more soft real-time nature. In this paper, we study the problem of minimizing energy for soft real-time systems while providing a QoS guarantee. The QoS requirements are deterministically quantified with the (m, k)-constraints, which require that at least m out of any k consecutive jobs of a task meet their deadlines. In this paper, we propose a hybrid approach to achieve the dual goals of QoS guarantee and energy minimization. We first present the necessary and sufficient schedulability conditions for the static mandatory/optional workload partitioning. Then, we propose to dynamically vary the statically defined mandatory/optional partitions to accommodate dynamic run-time variations while minimizing the energy consumption. The experimental results demonstrate that our proposed techniques outperform previous work significantly in terms of both the energy savings and achieved QoS.

关键词： dynamic volage scaling (DVS) earliest deadline first (EDF) embedded system quality of service (QoS) real-time scheduling

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Demand paging for OneNANDTM Flash eXecute-in-place

Demand paging for OneNANDTM Flash eXecute-in-place

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Yongseok Choi Eui-Young Chung Naehyuck Chang Sung Woo Chung Chanik Park Yongsoo Joo Seoul National University Korea Yonsei University Korea Samsung Electronics Korea Korea University Korea

NAND flash memory can provide cost-effective secondary storage in mobile embedded systems, but its lack of a random access capability means that code shadowing is generally required, taking up extra RAM space. Demand paging with NAND flash memory has recently been proposed as an alternative which requires less RAM. This scheme is even more attractive for OneNAND flash, which consists of a NAND flash array with SRAM buffers, and supports eXecute-ln-Place (XIP), which allows limited random access to data on the SRAM buffers. We introduce a novel demand paging method for OneNAND flash memory with XIP feature. The proposed on-line demand paging method with XIP adopts finite size sliding window to capture the paging history and thus predict future page demands. We particularly focus on non-critical code accesses which can disturb real-time code. Experimental results show that our method outperforms conventional LRU-based demand paging by 57% in terms of execution time and by 63% in terms of energy consumption. It even beats the optimal solution obtained from MIN, which is a conventional off-line demand paging technique by 30% and 40% respectively.

关键词： Random access memory Embedded system Read-write memory Energy consumption Memory management Algorithm design and analysis Permission system-on-a-chip Decoding User interfaces

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"It's a small world after all": NoC performance optimization via long-range link insertion

"It's a small world after all": NoC performance optimization...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Ogras, Umit Y. Marculescu, Radu Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental, results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.

关键词： design automation multiprocessor system-on-chip (MP-SoC) network-on-chip (NoC) performance analysis

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