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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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Multi-objective Q-bit coding genetic algorithm for hardware-software co-synthesis of embedded systems

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6th international conference on Simulated Evolution and Learning

作者： Wei Wen-long Li Bin Zou Yi Zhuang Zhen-quan Univ Sci & Technol China Nat Inspired Computat & Applicat Lab Hefei 230026 Peoples R China

ISBN: (纸本)3540473319

One of the key tasks in hardware-software Co-design is to optimally allocate, assign, and schedule resources to achieve a good balance among performance, cost, power consumption, etc. So it's a typical multi-objective optimization problem. In this paper, a Multi-objective Q-bit coding genetic algorithm (MoQGA) is proposed to solve HW-SW co-synthesis problem in HW-SW co-design of embedded systems. The algorithm utilizes the Q-bit probability representation to model the promising area of solution space, uses multiple Q-bit models to perform search in a parallel manner, uses modified Q-bit updating strategy and quantum crossover operator to implement the efficient global search, uses an archive to preserve and select pareto optima, uses Timed Task Graph to describe the system functions, introduces multi-PRI scheduling strategy and PE slot-filling strategy to improve the time performance of system. Experimental results show that the proposed algorithm can solve the multi-objective co-synthesis problem effectively and efficiently.

关键词： Genetic algorithms

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Cutting across layers of abstraction:: removing obstacles from the advancement of embedded systems

Cutting across layers of abstraction:: removing obstacles fr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Krisztian Flautner ARM Limited

Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This steady progress has created a sense of entitlement for the riches that future process generations would bring. Today, however, classical process scaling seems to be dead and living up to technology expectations requires continuous innovation at many levels, which comes at steadily progressing implementation and design costs. Solutions to problems need to cut across layers of abstractions and require coordination between software, architecture and circuit features. Heterogeneous multiprocessor clusters are increasingly used to deliver the required compute power for high-end applications. Heterogeneity ensures that the necessary processing power can be delivered at high levels of efficiency at reasonable implementation cost, while the use of processors endow these systems with large degrees of flexibility. One of the key challenges with these systems is system-level programming. Traditional compiler technologies are strong at programming individual cores but leave the task of parallelization to a team of experts. The first part of this talk will describe the coupling of the compiler to the system architecture on a multi-core signal-processing cluster and illustrate how compiler technology can enable the writing of portable parallel programs for it using little more than C. As claimed above, close coupling of abstraction layers can be beneficial. This can also be illustrated at the microarchitecture - circuit boundary. The second part of the talk will describe a prototype microarchitecture which is designed explicitly to deal with issues such as silicon variation and soft errors. These features in return enable system designers to focus on the typical-case performance of their implementations without having to be over-constrained by worst-case conditions.

关键词： Embedded system Program processors Silicon Costs Circuits Microarchitecture Energy consumption Power generation Technological innovation Computer architecture

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A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control

A buffer-sizing algorithm for networks on chip using TDMA an...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Andrei Ruadulescu Kees Goossens Giovanni De Micheli Srinivasan Murali Martijn Coenen Philips Research Eindhoven The Netherlands CSL Stanford University Stanford USA LSI Switzerland LSI EPFL Switzerland

When designing a system-on-chip (SoC) using a network- on-chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power consumption is due to the buffers in the network interfaces (NIs) needed to decouple computation from communication. Having such a decoupling prevents stalling of IP blocks due to the communication interconnect. The size of these buffers is especially important in real-time systems, as there they should be big enough to obtain predictable performance. To ensure that buffers do not overflow, end- to-end flow-control is needed. One form of end-to-end flow- control used in NoCs is credit-based flow-control. This form places additional requirements on the buffer sizes, because the flow-control delays need to be taken into account. In this work, we present an algorithm to find the minimal decoupling buffer sizes for a NoC using TDMA and credit- based end-to-end flow-control, subject to the performance constraints of the applications running on the SoC. Our experiments show that our method results in a 84% reduction of the total NoC buffer area when compared to the state-of- the art buffer-sizing methods. Moreover, our method has a low run-time complexity, producing results in the order of minutes for our experiments, enabling quick design cycles for large SoC designs. Finally, our method can take into account multiple usecases running on the same SoC.

关键词： Network-on-a-chip Time division multiple access Communication system control system-on-a-chip Energy consumption Silicon Design optimization Network interfaces Computer interfaces Computer networks

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Development of a training simulator for power system operation

Development of a training simulator for power system operati...

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10th World Multi-conference on systemics, Cybernetics and Informatics/12th international conference on Information systems Analysis and synthesis

作者： Cha, Seung-The Kim, Tae-Kyun Lee, Chul-Kyun Shin, Jeong-Hoon Choi, Jun-Ho Nam, Su-Chul Korea Elect Res Inst 103-16 Munji Dong Taejon 305380 South Korea LS Ind Syst Cheongju 361720 South Korea

ISBN: (纸本)9789806560680

A new type of simulation training system for power system operation is presented in this paper. It is based on transmission mimic board, double screen PC, mimic control panel, and real-time digital simulator, KEPS. The operating simulation includes the simulations of the control panel interface and the simulator. The mimic board displays transmission network summary information using a software view of the hardware based mimic board. The symbols, numbers and colors layout exactly match those of the KEPS draft case to provide operators a familiar and effective starting point. This paper describes the development of an innovative training system, utilizing the benefits of 3 dimension visualization s/w and communication-control s/w to create the appropriate operational environment and allow simulation of various power system operations without the restrictions of other training methods. Experiences gained in developing concepts and meeting considerable s/w challenges are outlined, and the potential of the simulator for future operations training discussed.

关键词： Simulators

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Energy minimization for real-time systems with (m, k)-guarantee

Energy minimization for real-time systems with (<i>m</i>, <i...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Niu, Linwei Quan, Gang Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Energy consumption and quality of service (QoS) are two primary concerns in the development of today's pervasive computing systems. While most of the current research in energy-aware real-time scheduling has been focused on hard real-time systems, a large number of practical applications and systems exhibit more soft real-time nature. In this paper, we study the problem of minimizing energy for soft real-time systems while providing a QoS guarantee. The QoS requirements are deterministically quantified with the (m, k)-constraints, which require that at least m out of any k consecutive jobs of a task meet their deadlines. In this paper, we propose a hybrid approach to achieve the dual goals of QoS guarantee and energy minimization. We first present the necessary and sufficient schedulability conditions for the static mandatory/optional workload partitioning. Then, we propose to dynamically vary the statically defined mandatory/optional partitions to accommodate dynamic run-time variations while minimizing the energy consumption. The experimental results demonstrate that our proposed techniques outperform previous work significantly in terms of both the energy savings and achieved QoS.

关键词： dynamic volage scaling (DVS) earliest deadline first (EDF) embedded system quality of service (QoS) real-time scheduling

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proceedings - Fourth ACM & IEEE international conference on Formal Methods and Models for Co-Design MEMOCODE'06

Proceedings - Fourth ACM & IEEE International Conference on ...

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4th ACM and IEEE international conference on Formal Methods and Models for Co-Design, MEMOCODE'06

ISBN: (纸本)1424404215

The proceedings contain 22 papers. The topics discussed include: games for formal design and verification of reactive systems;analyzing tabular requirements specifications using infinite state model checking;mixed symbolic representations for model checking software programs;low-power hardware synthesis from TRS-based specifications;scalable program analysis using boolean satisfiability;execution semantics and formalisms for multi-abstraction TLM assertions;a methodology for abstracting RTL designs into TL descriptions;using reo for formal specification and verification of system designs;specifying and proving properties of timed I/O automata in the TIOA toolkit;reliable design with multiple clock domains;the systemJ approach to system-level design;efficient code generation from synchronous programs;latency-insensitive design and central repetitive scheduling;and a scenario-aware data flow model for combined long-run average and worst-case performance analysis.

关键词： Formal methods

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Robust modelling of hard-disk drives servo system

Robust modelling of hard-disk drives servo system

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25th IASTED international conference on Modelling, Identification, and Control, MIC 2006

作者： Svecko, Rajko Pec, Martin University of Maribor Faculty of Electrical Engineering Smetanova 17 Maribor Slovenia

ISBN: (纸本)0889865515

This paper introduces a new method for modelling a hard disc VCM actuator. The results of this method are a nominal model, and the weighting functions for H∞ regulator synthesis. The hardware and software have been designed of automated read/write head position measurements according to referenced positions, different frequencies, and various temperatures. The measurement results represent the distribution functions of the read/write head position at each frequency. A differential evolution algorithm is used to determining the nominal model and weighting functions. This algorithm converges fast on a suitable functional selection. The proposed method is illustrated sequentially through the experimental example. On the basis of the experimental results the H∞ robust controller was designed.

关键词： Optimization

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A Methodology for Generating Application-Specific Heterogeneous Processor Arrays

A Methodology for Generating Application-Specific Heterogene...

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Annual Hawaii international conference on system Sciences (HICSS)

作者： S. Craven C. Patterson P. Athanas Virginia Polytechnic Institute and State University USA

hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the chip’s array of processors can be tailored to their program, creating an application-specific multiprocessor. While much hardware/software codesign research has been conducted on optimizing heterogeneous processing arrays, shortcomings exist in design scalability, simulation, verification, rapid prototyping, and the requirement of specialized skill sets. To address these deficiencies, a design methodology is proposed targeting signal processing applications that maps a parallelized C program onto a homogenous array of processors linked by simple point-to-point connections. By individually optimizing each processor for its specific program the performance of the array is increased, while the common basic interface between processors eases optimization, implementation, debugging, and verification.

关键词： hardware Application software Turning Throughput Design optimization Scalability software prototyping Virtual prototyping Design methodology Array signal processing

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Architecture of a Search Engine for Massive Comparison in an Iris Biometric system

Architecture of a Search Engine for Massive Comparison in an...

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international Carnahan conference on Security Technology

作者： Judith Liu-Jimenez Raul Sanchez-Reillo Almudena Lindoso John G. Daugman Department Electronic Technology-Microelectronics Group Universidade Carlos III de Madrid Leganes Spain Spain Computer Laboratory University of Cambridge Cambridge UK

Biometrics is becoming one of the techniques most used for identification. Although these techniques are quite suitable for this purpose, when massive identification is required no for all of them there are dedicated devices. In this paper, the authors propose three different architectures for a search engine based on iris biometrics. These architectures relays on hardware-software codesign, reducing the expected time of comparison and the equipment cost

关键词： Search engines Biometrics Computer architecture Costs Security hardware Iris recognition Microelectronics Relays Identity management systems

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A codesign Tool for High Level Systhesis of Vision Models on FPL

A Codesign Tool for High Level Systhesis of Vision Models on...

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international conference on Field Programmable Logic and Applications

作者： Antonio Martinez Leonardo Reynery Francisco Pelayo Christian Morillas Samuel Romero Department of Computing Technology University of Alicante Spain Department of Electronics Polytechnic of Torino Italy Department of Computer Engineering University of Granada Spain Department of Computer Sciences University of Jaen Spain

This paper presents a synthesis tool for the automatic translation and optimization of bioinspired vision models into a FPL implementation. The software allows functional simulation and high level specification of the model, and produces a data-flow model using VHDL, which is synthesizable with different lower-level synthesis tools and for various FPGA technologies. The proposed design platform extends the features of the codesign environment CodeSimulink for implementing visual processing systems, starting from purely functional specifications. An optimization strategy based on the calculation of the Pareto front is also introduced to perform a multi-objective minimization of both, the circuit area and the root mean square of the computation error. Performance measurements for the FPL implementation of an example retina-like vision model on a FPGA-based PCI board are provided

关键词： Mathematical model Computer vision Field programmable gate arrays Computational modeling Power system modeling hardware Real time systems Filters Design engineering Knowledge engineering

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