Historically, software application systems have been produced either individually tailored for the specific customer, or they have been adapted from standardized packages. This paper proposes that component based soft...
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Historically, software application systems have been produced either individually tailored for the specific customer, or they have been adapted from standardized packages. This paper proposes that component based software development could provide a synthesis of both approaches, combining the best aspects of each of the other two paradigms. Taking a closer look at the underlying principles of software reuse and modularity, however, reveals a number of conflicting forces that influence the acceptance and diffusion of this new paradigm within and throughout the software industry. A dialectical change perspective is used to explain this change process. It is argued that traditional software producers have a dominant position in their industry, and will be able to retain this position for some time. However, the concept of mindful innovation is introduced to give an outlook how smaller software producers might exploit the opportunities that this paradigm shift provides.
Sliding window algorithms are fundamental parts of each image processing system. Especially those belonging to the class of static algorithms offer various possibilities for analysis and optimization. Only if this pot...
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Sliding window algorithms are fundamental parts of each image processing system. Especially those belonging to the class of static algorithms offer various possibilities for analysis and optimization. Only if this potential is exploited, a high level synthesis of such algorithms will lead to efficient implementations. Such an analysis relies on an efficient representation by a well-defined model of computation. It must abstract important properties of sliding windows as for instance the relation between input and output data as well as the required buffer space. In this paper, a corresponding static model of computation for sliding window algorithms is elaborated, called windowed synchronous data flow (WSDF). Its main focus lies on applications with two or more dimensions. Furthermore, the WSDF balance equation is derived allowing to verify bounded token accumulation during execution
The proceedings contain 45 papers from the internationalconference on hardware/softwarecodesign and systemsynthesis, CODES+ISSS 2004. The topics discussed include: future challenges in embedded systems;dual-pipelin...
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ISBN:
(纸本)1581139373
The proceedings contain 45 papers from the internationalconference on hardware/softwarecodesign and systemsynthesis, CODES+ISSS 2004. The topics discussed include: future challenges in embedded systems;dual-pipeline heterogeneous ASIP design;hardwaresynthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis;memory accesses management during high level synthesis;benchmark-based design strategies for single chip heterogeneous multiprocessors;dynamic overlay of scratchpad memory for energy minimization;power-performance trade-offs for reconfigurable computing;and facilitating reuse in hardware models with enhanced type inference.
No two flight missions are alike, hence, development and on-orbit software costs are high. software portability and adaptability across hardware platforms and operating systems has been minimal at best. Standard inter...
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ISBN:
(纸本)1595931619
No two flight missions are alike, hence, development and on-orbit software costs are high. software portability and adaptability across hardware platforms and operating systems has been minimal at best. Standard interfaces across applications and/or common applications are almost non-existent. To reduce flight software costs, these issues must be addressed. This presentation describes how the Flight software Branch at Goddard Space Flight Center has architected a solution to these problems.
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing architectural synthesis approaches in orde...
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ISBN:
(纸本)1595931619
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing architectural synthesis approaches in order to apply global optimization techniques across process bounds for shared system resources (e.g. memories, busses, global ALUs) during scheduling and binding. This allows an area efficient implementation of un-timed or cycle-fixed multiprocess specifications at RT or algorithmic level of abstraction. Furthermore, this approach supports environment-oriented synthesis for optimized module integration by scheduling accesses to global resources with respect to the access schedules of other modules communicating to the same global resources. As a result, dynamic access conflicts can be avoided by construction, and hence, there is no need for dynamic arbitration of bus and memory accesses with potentially unpredictable timing behavior.
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom design techniques for digital microfluid...
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ISBN:
(纸本)1595931619
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom design techniques for digital microfluidic biochips do not scale well for increasing levels of system integration. Analogous to classical VLSI synthesis, a top-down system-level design automation approach can shorten the biochip design cycle and reduce human effort. We present here an overview of a system-level design methodology that includes architectural synthesis and physical design. The proposed design automation approach is expected to relieve biochip users from the burden of manual optimization of bioassays.. time-consuming hardware design, and costly testing and maintenance procedures.
There are several approaches to the hardware/software design in embedded systems, ranging from the traditional sequential methods which focus on the determination of the hardware architecture prior to software design,...
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ISBN:
(纸本)0769524133
There are several approaches to the hardware/software design in embedded systems, ranging from the traditional sequential methods which focus on the determination of the hardware architecture prior to software design, to newer object-oriented approaches that attempt to apply software engineering methods to hardware design without a systematic process. This paper discusses a structured object-oriented methodology for the integrated co-analysis and co-design of hardware/softwaresystems using an extended High Order Object-oriented Modeling Technique (HOOMT). This methodology offers a uniform method for hardware and software developers to jointly develop the specifications for and partitioning of the hardware and software components of a system, as well as developing the interfaces between components, and allows easy design migration of components between hardware and software. In this paper it is applied to the co-analysis/co-design of the hardware and software of a simulated advanced power grid control system.
This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image proces...
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ISBN:
(纸本)1595931619
This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGA board. Two automotive and two mobile smart imaging applications are mapped onto the resulting smart imaging core. This mapping process of the original C++ applications onto the smart imaging core is also presented in this paper.
We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application's binary are competitive with partitioning at the C source code level. ...
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ISBN:
(纸本)1595931619
We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application's binary are competitive with partitioning at the C source code level. While such competitiveness has been shown previously for standard benchmark suites involving smaller or unoptimized applications, the case study instead focuses on a complete 16,000-line highly-optimized commercial-grade application, namely an H.264 video decoder. The several month study revealed that binary partitioning was indeed competitive, achieving nearly identical 2.5x speedups as source level partitioning, compared to a standard microprocessor. Furthermore, the study revealed that several simple C-level coding modifications, including pass by value-return, function specialization, algorithmic specialization, hardware-targeted reimplementation, global array elimination, hoisting and sinking of error code, and conversion to explicit control flow, could lead to improved application speedups approaching 7x for both source level and binary level partitioning.
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