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Implementation of dynamic streaming applications on heterogeneous multi-processor architectures 05

Implementation of dynamic streaming applications on heteroge...

引用

international conference on hardware/software codesign and system synthesis

作者： Henriksson, T Kang, J van der Wolf, P Philips Res NL-5656 AE Eindhoven Netherlands

ISBN: (纸本)1595931619

system design based on static task graphs does not match well with modem consumer electronic devices with dynamic stream processing applications. We propose the TTL API for task graph reconfiguration services, which can be used to describe the dynamic behaviour of applications. We demonstrate the efficient implementation of the TTL A-PI on a heterogeneous multi-processor architecture. It is possible to design dynamic streaming applications with reusable reconfiguration-aware tasks and we argue that the TTL API serves as a good starting point for standardization.

关键词： system level design dynamic applications platform interface

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A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications 05

A system-level methodology for fully compensating process va...

引用

international conference on hardware/software codesign and system synthesis

作者： Papanikolaou, A Lobmaier, F Wang, H Miranda, M Catthoor, F IMEC vzw Louvain Belgium

ISBN: (纸本)1595931619

Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to variability in the conventional design process. It is based on offering configuration capabilities at the memory-level and exploiting them at the system-level. This technique can decrease by up to a factor of 5 the energy overhead that is introduced by state-of-the-art process variability compensation techniques, including statistical timing analysis. In this way we obtain results close to the ideal nominal design again.

关键词： process variability system-level compensation parametric yield

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A UAV-based computer engineering capstone senior design project

A UAV-based computer engineering capstone senior design proj...

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IEEE international conference on Microelectronic systems Education

作者： Klenke, RH Virginia Commonwealth Univ Dept Elect Engn Richmond VA 23284 USA

ISBN: (纸本)0769523749

This paper describes the development of an Unmanned Aerial Vehicle (UAV) for a capstone senior design project in computer engineering. The student portion of the project involved the development of a flight control system for the UAV The flight control system was based on the Atmel FPSLIC device. The FPSLIC contains an 8-bit A T R microcontroller and a 40K gate-equivalent Field Programmable Gate Array which allowed the students to implement components of the flight control system in both hardware and software. The overall system architecture and implementation of the flight control system are described.

关键词： aircraft control computer science education control system synthesis engineering education field programmable gate arrays hardware-software codesign microcontrollers student experiments FPGA capstone senior design project computer engineering field progr Field programmable gate arrays Flight control systems COMPUTER ENGINEERING Aircraft control Microcontrollers Student experiments hardware/software co-design control system synthesis computer science education Engineering education

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Power-smart system-on-chip architecture for embedded cryptosystems 05

Power-smart system-on-chip architecture for embedded cryptos...

引用

international conference on hardware/software codesign and system synthesis

作者： Muresan, R Vahedi, H Zhanrong, Y Gregori, S Univ Guelph Sch Engn Guelph ON N1G 2W1 Canada

ISBN: (纸本)1595931619

In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provides support for masking these channels by controlling, in real-time, the power and the current consumption of a system to predefined programmable values. The main components of the architecture are a processor core, a current sensor module, a dynamically controlled power supply module, a clock frequency control module, and a current injection module. Real-time current measurements and power-aware voltage control are used in closed loop architecture to regulate and minimize the total power consumption of the system. Simulation results show that the current consumption of the system can be regulated to a reference level with reduced power-to-security trade off (power overhead less than 12% of the total power).

关键词： power-smart system-on-chip power analysis attack resistant architecture current flattening in hardware voltage scaling DES

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Future wireless convergence platforms

Future wireless convergence platforms

引用

international conference on hardware/software codesign and system synthesis

作者： Glossner, J Moudgill, M Iancu, D Nacer, G Jintukar, S Stanley, S Samori, M Raja, T Schulte, M Vassiliadis, S Sandbridge Technol Inc White Plains NY 10601 USA

ISBN: (纸本)1595931619

As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, support for signal processing (both audio and video), control code, and Java execution will be required in a convergent device. Traditionally, wireless communications systems have been implemented in hardware. Convergent devices must be able to roam seamlessly across multiple communications systems. To avoid excessive hardware costs, a software Defined Radio (SDR) approach offers a programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing. In this paper, we discuss trends in wireless platforms which are inherently convergence platforms. We also present the Sandbridge state-of-the-art example platform that supports both communications and multimedia applications processing. The architecture efficiently executes Java, Digital Signal Processing (DSP), and control code. Architectural features that reduce power dissipation and enable real-time processing are described. All of the communications and multimedia processing is executed completely in software without specialized hardware support. The processor is programmed in C with supercomputer-class compiler support for automatic vectorization, multithreading, and DSP semantic analysis.

关键词： software defined radio wireless digital signal processors

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The challenges of embedded system design

The challenges of embedded system design

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3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Muller, Mike ARM

ISBN: (纸本)1595931619

As complexity grows the importance of system level exploration, design, verification and debug becomes inescapable. However while there has been great progress in process technology, tools and methodologies resulting in ever more sophisticated platforms some of the critical design parameters have been moving in the wrong direction. Power is becoming a critical challenge that will require new solutions for both design and manufacturing if the roller coaster ride is to continue.

关键词： Embedded systems

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system design extreme makeover 05

System design extreme makeover

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3rd ACM/IEEE international conference on Formal Methods and Models for Co-Design

作者： Gajski, DD Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)0780392272

With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. In order to find a solution for the system-level design flow, we must look at the system gap between SW and HW designs and then try to bridge this gap by developing a design flow that is based on common principles applicable to software and hardware. In order to achieve this design flow we can define design process by using the concepts found in standard algebras which, in turn, allows us to define design models more formally with clean unambiguous semantics. Such clean semantics allows automatic model generation, simplifies synthesis algorithms and verification techniques.

关键词： system-level design flow formal verification technique hardware-software codesign automatic model generation

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FlexPath NP - A network processor concept with application-driven flexible processing paths

FlexPath NP - A network processor concept with application-d...

引用

international conference on hardware/software codesign and system synthesis

作者： Ohlendorf, R Herkersdorf, A Wild, T Tech Univ Munich D-80290 Munich Germany

ISBN: (纸本)1595931619

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based system on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

关键词： network processors application-specific architectures hardware accelerators dynamically reconfigurable processors IP networking

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What will system level design be when it grows up? 05

What will system level design be when it grows up?

引用

international conference on hardware/software codesign and system synthesis

作者： Martin, G Gajski, D Goodwin, D Lysaght, P Marwedel, P Muller, M Weiser, J Tensilica UC Irvine Xilinx Research University of Dortmund Germany ARM UK IBM

ISBN: (纸本)1595931619

We have seen a growing new interest in Electronic system Level (ESL) architectures, design methods, tools and implementation fabrics in the last few years. But the picture of what types and approaches to building embedded systems will become the most widely-accepted norms in the future remains fuzzy at best. Everyone want to know where systems and system design is going "when it grows up", if it ever "grows up". Some of the key questions that need to be answered include which applications will be key system drivers, what SW & HW architectures will suit best, how programmable and configurable will they be, will systems designers need to deal with physical implementation issues or will that be hidden behind fabric abstractions and programming models, and what will those abstractions and models be? Moreover, will these abstractions stabilize and be still useful as the underlying technology keeps developing at high *** panel consists of proponents of a number of alternative visions for where we will end up, and how we will get there.

关键词： system-level compensation parametric yield process variability

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A unified approach to constrained mapping and routing on network-on-chip architectures 05

A unified approach to constrained mapping and routing on net...

引用

international conference on hardware/software codesign and system synthesis

作者： Hansson, A Goossens, K Radulescu, A Lund Univ Dept Informat Technol S-22100 Lund Sweden

ISBN: (纸本)1595931619

One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach.

关键词： system-on-chip network-on-chip quality-of-service mapping routing

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