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Revolution in electronic EDA education/research: GOSPL

Revolution in electronic EDA education/research: GOSPL

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IEEE international conference on Microelectronic systems Education

作者： Sud, R Chaitanya, M ST Microelect Pvt Ltd Noida India

ISBN: (纸本)0769523749

This paper discusses how GOSPL (Generalized Open Source Programmable Logic), the world's first and only complete, commercially viable hardware/software electronics platform is a dramatic and major step forward in Semiconductor & Electronic Design Automation Education/Research worldwide. Never before in the history of the world, the work of 300 people over 5 years representing over one million lines of EDA software code and correspondingly programmable system on chip Semiconductor IP Architecture have been made available to the global University system. It allows global education, research, innovation and entrepreneurialism for universities to play commercially viable EDA and VLSI IP game.

关键词： VLSI electronic design automation electronic engineering education field programmable gate arrays hardware-software codesign industrial property public domain software system-on-chip EDA GOSPL Generalized Open Source Programmable Logic education ele

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Highly flexible multi-mode system synthesis 05

Highly flexible multi-mode system synthesis

引用

3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Kumar, Vinu Vijay Lach, John Texas Instruments M/S 714 12203 Southwest Fr. Stafford TX 77477 United States Department of Electrical and Computer Engineering University of Virginia 351 McCormick Rd. Charlottesville VA 22904 United States

ISBN: (纸本)1595931619

Multi-mode systems have emerged as an area- and power-efficient approach to implementing multiple time-wise mutually exclusive algorithms and applications in a single hardware space. These systems have limited flexibility and temporal separation between modes is achieved by changing only the dataflow between components. This paper presents a synthesis methodology for integrating flexible components and controllers into primarily fixed logic multi-mode systems thereby increasing their overall flexibility and efficiency. The components are built using a technique called small-scale reconfigurability that provides the necessary flexibility without the penalties associated with generalpurpose reconfigurable logic. The reconfiguration latency is small enabling both inter-mode and intra-mode reconfiguration of components. Datapath and controller area and power consumption are reduced beyond what is provided in current multi-mode systems using this methodology, without sacrificing performance. The results show an average 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and a 68% reduction in the number of controller signals for a set of benchmark 32-bit signal processing applications. There is also an average 38% increase in component utilization. Copyright 2005 ACM.

关键词： Algorithms

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Enhancing security through hardware-assisted run-time validation of program data properties 05

Enhancing security through hardware-assisted run-time valida...

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3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Arora, Divya Raghunathan, Anand Ravi, Srivaths Jha, Niraj K. Dept. of Electrical Engineering Princeton University Princeton NJ 08544 United States NEC Laboratories America Princeton NJ 08540 United States

ISBN: (纸本)1595931619

The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This is particularly relevant in the embedded domain, where the security solution should be customized to the needs of the target system, while considering other design objectives such as cost, performance, and power. Due to the increasing complexity and shrinking design cycles of embedded software, most embedded systems present a host of software vulnerabilities that can be exploited by security attacks. Many attacks are initiated by causing a violation in the properties of data (e.g., integrity, privacy, access control rules, etc.) associated with a "trusted" program that is executing on the system, leading to a range of undesirable effects. In this work, we develop a general framework that provides security assurance against a wide class of security attacks. Our work is based on the observation that a program's permissible behavior with respect to data accesses can be characterized by certain properties. We present a hardware/software approach wherein such properties can be encoded as data attributes and enforced as security policies during program execution. These policies may be application-specific (e.g., access control for certain data structures), compiler-generated (e.g., enforcing that variables are accessed only within their scope), or universally applicable to all programs (e.g., disallowing writes to unallocated memory). We show how an embedded system architecture can support, such policies by (i) enhancing the memory hierarchy to represent the attributes of each datum as security tags that are linked to it through its lifetime, and (ii) adding a configurable hardware checker that interprets the semantics of the tags and enforces the desired security policies. We evaluated the effectiveness of the proposed architecture in enforcing various security policies for several embedded bench

关键词： Data reduction

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High-level synthesis for large bit-width multipliers on FPGAs: A case study

High-level synthesis for large bit-width multipliers on FPGA...

引用

3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Quan, Gang Davis, James P. Devarkal, Siddhaveerasharan Buell, Duncan A. Department of Computer Science and Engineering University of South Carolina Columbia SC 29208 United States

ISBN: (纸本)1595931619

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource cost-effectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform. Copyright 2005 ACM.

关键词： Field programmable gate arrays

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On ensuring safety and liveness properties of concurrent models in systemC

On ensuring safety and liveness properties of concurrent mod...

引用

IEEE international conference on Microelectronic systems Education

作者： Shurpali, P Shankar, R Shuff, E Florida Atlantic Univ Boca Raton FL 33431 USA

ISBN: (纸本)0769523749

Potential for reuse and performance improvement have motivated multi-threaded, multi-core applications on current SoCs (system on a Chip). Concurrency has thus surfaced as a major challenge in SoC Traditional design and verification approaches will not be cost-effective in exposing concurrency failures;this inability can lead to significantly increased time to market and field failures. To test for concurrency problems early on, one would have to develop abstract concurrency models and do exhaustive analysis on these models. We discuss in this paper a graduate course on concurrency modeling where we used such abstract concurrency models prior to coding. For use in software-hardware co-design, we integrated this modeling methodology with systemC. We have documented the results with several examples.

关键词： C++ language computer science education concurrency control educational courses hardware-software codesign multi-threading system-on-chip systems analysis C++ based system level modeling SoC concurrency systemC modeling abstract concurrency models concur Concurrency Model system-on-chip Multithreading hardware/software co-design C language Concurrency control computer science education Education courses system analyses Concurrency

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hardware and software architectures for the Cell processor 05

Hardware and software architectures for the Cell processor

引用

3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Hofstee, Peter Day, Michael IBM Systems and Technology Group Austin TX United States

ISBN: (纸本)1595931619

The Cell processor is a first instance of a new family of processors intended for the broadband era. The processors will find early use in game systems (PlayStation3™), a variety of other consumer electronics applications, a wide variety of embedded applications, and various forms of computational accelerators. Cell is a non-homogeneous multi-core processor, with one POWER processor core (two threads) dedicated to the operating system and other control functions, and eight synergistic processors optimized for compute-intensive applications. Cell addresses two of the main limiters to microprocessor performance: increased memory latency, and performance limitations induced by system power limits. Memory latency is addressed by introducing another software-managed level of private "local" memory, in between the private registers and shared system memory. Data is transferred between this local memory and shared memory with asynchronous cache coherent DMA commands, and synergistic processor load and store commands access the local store only. This organization of memory makes it possible for the Cell processor to have over 100 memory transactions in flight at the same time, more than enough to cover memory latency. Power limitations are addressed by two main mechanisms;a non-homogeneous multi-core organization, and an ultra high-frequency design that allows the chip to be operated at 3.2GHz at low voltage. The Cell processor supports many of today's programming models by introducing the concept of heterogeneous tasks or threads. Both Power processor and SPE based threads can be managed by the operating system and effectively utilized by applications starting with the relatively straightforward function offload model to the more complex single source heterogeneous parallel programming model. Cell achieves between one and two orders of magnitude of performance advantage over conventional single-core processors on compute-intensive (32-bit) applications, by permitting progr

关键词： Computer architecture

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hardware-software codesign of a fingerprint identification algorithm

引用

5th international conference on Audio- and Video-Based Biometric Person Authentication

作者： Canyellas, N Cantó, E Forte, G López, M Escola Tecn Super Engn ETSE URV Tarragona Spain

ISBN: (纸本)3540278877

Automatic Fingerprint Authentication systems are rapidly being incorporated in a wide range of applications, satisfying the society demand of accurate identification frameworks in order to prevent unauthorised accesses or fraudulent uses. Most of biometrics based personal identification systems run on high-performance computer based platforms, which execute a set of complex algorithms implemented in software. Those solutions cannot be applied to small, low-cost and low-power embedded systems, based on microprocessors without floating-point arithmetic unit. In this article we present a hardware/software implementation of a fingerprint minutiae extraction algorithm. The proposed system consists of a microprocessor and a coprocessor implemented in an associated FPGA. In order to develop an efficient implementation, fixed-point computations have substituted the floating-point ones. Due to the low feature requirements the whole system is suitable for a SoC with embedded flexible hardware.

关键词： Pattern recognition

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FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals

FIDES: An advanced chip multiprocessor platform for secure n...

引用

3rd IEEE/ACM/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Inoue, Hiroaki Ikeno, Akihisa Kondo, Masaki Sakai, Junji Edahiro, Masato System Devices Research Laboratories NEC Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan NEC Informatec Systems Ltd. 3-2-1 Sakado Kawasaki Kanagawa 213-0012 Japan

ISBN: (纸本)1595931619

We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multi-grained separation mechanisms: coarse-grained processor-level separation of the basic-function domain from other domains for such downloaded applications, medium-grained OS-level separation, and fine-grained process-level separation within SELinux. Four new technologies, which include three enhancements to SELinux, support the FIDES platform: 1) bus filter logic for processor-level separation can be implemented as a small logic, 2) XIP kernels for memory-efficient OS-level separation can reduce memory requirements by 182%, 3) policy separation for enhanced process-level separation can apply policies 2.1 times faster at system bootup, and 4) dynamic access control can provide secure Inter-Domain Communications (IDCs) with an overhead of only 4% for IDC system calls. We implemented SELinuxes on an ARM-based multiprocessor. Therefore, the best-suited platform to secure next generation mobile terminals is the FIDES platform, which can provide higher security as well as higher performance and lower power consumption on chip multiprocessors leading the current technology trend of microprocessors. Copyright 2005 ACM.

关键词： Microprocessor chips

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Deterministic hardware synthesis for compiling high-level descriptions to heterogeneous reconfigurable architectures

Deterministic hardware synthesis for compiling high-level de...

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38th Annual Hawaii international conference on system Sciences, HICSS 2005

作者： Sullivan, Chris Wilson, Alex Chappell, Stephen

LUT based reconfigurability is being complemented with a new, emerging class of reconfigurable technology based on ALU and heterogeneous architectures. Moreover, existing FPGA technology has experienced recent advances that go beyond other implementation technologies such as DSP, ASIC or ASSP. Already deployed within the network infrastructure and application areas where performance, power and flexibility are principal, the migration of software-programmed hardware reconfigurability to the mobile computing domain is attractive. To enable this migration an advance in design automation is required where algorithms can be efficiently mapped to the computational fabric using software-programming techniques. In this paper we describe how digital circuits from software designs and formal executable specifications can be synthesized to reconfigurable architectures using higher-level languages and deterministic hardware compilation, or 'C-synthesis'. For context we provide an introduction and overview to reconfigurable architectures.

关键词： Computer hardware

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Developing design tools for biological and biomedical applications of micro- and nano-technology

Developing design tools for biological and biomedical applic...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jacob White Electrical Engineering and Computer Science Research Laboratory of Electronics Massachusetts Institute of Technology Cambridge MA USA

This short paper, an update of [75], is intended to provide a brief summary and extensive references on biological applications for micro- and nano-machining, as well as the computer-aided design challenges generated ... 详细信息

关键词： Nanobioscience Design automation Nanoscale devices Micromechanical devices Nanoelectromechanical systems Application software Electrostatics Biology Gene expression Prototypes

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