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A system-level architecture for hash message authentication code

A system-level architecture for hash message authentication ...

引用

12th IEEE international conference on Electronics, Circuits and systems, ICECS 2005

作者： Khali, H. Mehdi, R. Araar, A. Ajman University of Science and Technology PO.BOX 346 Ajman United Arab Emirates

ISBN: (纸本)9789972611001

Modern network-based applications continuously raise the demand for secure data communications. This demand has motivated the development of new cryptographic standards and encryption algorithms. The hash message authentication code (HMAC) has been adopted as a standard for robust authentication with enhanced security features. HMAC makes use of well-known hash functions. Hash function security levels have been considerably improved by introducing a new standard, named SHA-2. The major strength of the new SHA-2 standard relies in its variable-size hash value (256, 384, 512 bits). In this paper, a new system architecture is proposed to implement HMAC using SHA-2 hash functions. This architecture aims to maximize the throughput and it follows a codesign approach, where the critical computations of SHA-2 hash algorithms are implemented in hardware, while the non-critical ones are kept in software. Finally, the proposed architecture is very flexible and can efficiently implement complex digital signature algorithms and keyed-hash message authentication codes.

关键词： Hash functions

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Enhanced code density of embedded CISC processors with echo technology

Enhanced code density of embedded CISC processors with echo ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Mauricio Breternitz Herbert Hum Ramesh Peri Jay Pickett Youfeng Wu INTEL Research Laboratory Santa Clara CA USA Low Power Microprocessor Laboratory INTEL Research Laboratory Santa Clara CA USA Compiler Laboratory INTEL Research Laboratory Santa Clara CA USA

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty.

关键词： Thumb Performance loss Reduced instruction set computing Program processors Costs Design optimization Optimizing compilers Embedded system Permission Microprocessors

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Using minimal minterms to represent programmability

Using minimal minterms to represent programmability

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Kurt Keutzer Scott J. Weber Electronics Research Laboratory University of California Berkeley USA

We address the problem of formally representing the programmability of a system. We define the programmability of a system as the set of valid execution paths that can be configured statically by software. We formally represent this programmability as a Boolean function. From this representation, we extract a subset of on-set minterms that we call minimal minterms. We prove that these minimal minterms represent the set of smallest schedulable atomic actions of the system, and that we can use a special generator relation to determine if subsets of these actions can be executed in parallel. We also prove that given an arbitrary Boolean function we can extract the minimal minterms and recreate the entire on-set by applying the generator relation to every element of the power set of the set of minimal minterms. Thus, the minimal minterms represent the complete instruction set supported by the system, and the generator relation represents the inherent parallelism among the instructions. Furthermore, we automatically generate the required software development tools and hardware implementation from this representation of programmability. Finally, we show that we can efficiently compute the minimal minterms and apply the generator relation to verify parallel executions on interesting data path systems.

关键词： Boolean functions Instruction sets Scheduling Computer aided instruction Power generation Parallel processing Programming hardware Data mining Algorithm design and analysis

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FlexPath NP: a network processor concept with application-driven flexible processing paths

FlexPath NP: a network processor concept with application-dr...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Andreas Herkersdorf Thomas Wild Rainer Ohlendorf Munich University of Technology Munich Germany

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based system on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

关键词： hardware Throughput Very large scale integration Virtual private networks DSL Computer architecture Permission Performance analysis Coprocessors Network interfaces

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SOMA: a tool for synthesizing and optimizing memory accesses in ASICs

SOMA: a tool for synthesizing and optimizing memory accesses...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Seth Copen Goldstein Tiberiu Chelcea Tobias Bjerregaard Girish Venkataramani Carnegie Mellon University Pittsburgh USA TU Denmark Lyngby Denmark

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance.

关键词： Network synthesis Delay Integrated circuit synthesis Large-scale systems Application specific integrated circuits High level synthesis Concurrent computing Throughput hardware design languages Libraries

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A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications

A system-level methodology for fully compensating process va...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： H. Wang M. Miranda F. Lobmaier F. Catthoor A. Papanikolaou IMEC vzw Leuven Belgium Katholieke Universiteit Leuven Leuven Belgium

Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to variability in the conventional design process. It is based on offering configuration capabilities at the memory-level and exploiting them at the system-level. This technique can decrease by up to a factor of 5 the energy overhead that is introduced by state-of-the-art process variability compensation techniques, including statistical timing analysis. In this way we obtain results close to the ideal nominal design again.

关键词： Timing Energy consumption Degradation Delay Process design Integrated circuit yield Robustness Runtime Permission Control systems

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An architectural level design methodology for embedded face detection

An architectural level design methodology for embedded face ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： R. Chellappa S. S. Bhattacharyya S. Saha W. Wolf G. Aggarwal J. Schlessman V. Kianzad ECE Department and Institute for Advanced Computer Studies University of Maryland College Park MD USA Department of Electrical Engineering Princeton University Princeton NJ USA

Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, including banking and security system access control, video surveillance, and multimedia information retrieval. In this paper, we discuss an architectural level design methodology for implementation of an embedded face detection system on a reconfigurable system on chip. We present models for performance estimation and validate these models with experimental values obtained from implementing our system on an FPGA platform. This modeling approach is shown to be efficient, accurate, and intuitive for designers to work with. Using this approach, we present several design options that trade-off various architectural features.

关键词： Design methodology Face detection Face recognition Banking Information security Access control Video surveillance Multimedia systems Information retrieval system-on-a-chip

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A unified approach to constrained mapping and routing on network-on-chip architectures

A unified approach to constrained mapping and routing on net...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Kees Goossens Andrei Radulescu Andreas Hansson Department of Information Technology Lund University Lund Sweden Philips Research Laboratories Eindhoven Netherlands

One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach.

关键词： Routing Network-on-a-chip Computer architecture Laboratories Network topology Runtime Decoding system-on-a-chip Delay Measurement

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The design of a smart imaging core for automotive and consumer applications: a case study

The design of a smart imaging core for automotive and consum...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Ghiath Alkadi Victor Reyes Bruno Steux Jorn Jochalsky Thomas Hinz Winfried Gehrke Wido Kruijtzer Philips Research Eindhoven The Netherlands Philips Semiconductors Hamburg Germany University of Las Palmas GC Spain University of Hannover Germany École des Mines de Paris France

This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGA board. Two automotive and two mobile smart imaging applications are mapped onto the resulting smart imaging core. This mapping process of the original C++ applications onto the smart imaging core is also presented in this paper.

关键词： Automotive engineering Coprocessors Radar detection Vehicle detection Smart cameras Image processing High level synthesis Signal processing algorithms Face detection Telephony

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Retargetable generation of TLM bus interfaces for MP-SoC platforms

Retargetable generation of TLM bus interfaces for MP-SoC pla...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Heinrich Meyr Rainer Leupers Achim Nohl Gerd Ascheid Tim Kogel Tom Michiels Andreas Wieferink Integrated Signal Processing Systems RWTH Aachen University Germany Coware Inc. CA USA

In order to meet flexibility, performance and energy efficiency constraints, future SoC (system-on-Chip) designs will contain an increasing number of heterogeneous processor cores combined with a complex communication architecture. Optimal platforms are obtained by customizing both computation and communication modules to the application's needs. In our design flow both kinds of SoC modules are automatically derived from abstract specifications. This work focuses on generating the communication adaptors, which are tailored to the processor as well as to the bus side. For early system simulation, the adaptors are capable of bridging an abstraction gap by implementing a bus interface state machine. The generated processor cores, adaptors and bus nodes are applied in the exemplary design of a JPEG decoding platform.

关键词： Energy efficiency Analytical models Computational modeling Interface states Network-on-a-chip Permission Signal generators Signal processing system-on-a-chip Computer architecture

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