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Power optimization for universal hash function data path using divide-and-concatenate technique

Power optimization for universal hash function data path usi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ramesh Karri Bo Yang Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

We present an architecture level low power design technique called divide-and-concatenate for universal hash functions based on the following observations: (i) the power consumption of a w-bit array multiplier and associated universal hash data path decreases as O(w4) if its clock rate remains constant. (ii) two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach we divide a w-bit data path (with collision probability 2-w) into two/four w/2-bit data paths (each with collision probability 2-w/2) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2-w). A popular low power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.

关键词： hardware Energy consumption Clocks Design optimization Computer architecture Authentication Iterative algorithms Power system reliability Arithmetic Logic design

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Future wireless convergence platforms 05

Future wireless convergence platforms

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Mayan Moudgill Michael Schulte Stamatis Vassiliadis Daniel Iancu Gary Nacer Michael Samori Sanjay Jintukar Stuart Stanley Tanuj Raja John Glossner Sandbridge Technologies Inc. White Plains NY USA Sandbridge Technologies Inc. White Plains NY

ISBN: (纸本)9781595931610

As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, support for signal processing (both audio and video), control code, and Java execution will be required in a convergent device. Traditionally, wireless communications systems have been implemented in hardware. Convergent devices must be able to roam seamlessly across multiple communications systems. To avoid excessive hardware costs, a software Defined Radio (SDR) approach offers a programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing. In this paper, we discuss trends in wireless platforms which are inherently convergence platforms. We also present the Sandbridge state-of-the-art example platform that supports both communications and multimedia applications processing. The architecture efficiently executes Java, Digital Signal Processing (DSP), and control code. Architectural features that reduce power dissipation and enable real-time processing are described. All of the communications and multimedia processing is executed completely in software without specialized hardware support. The processor is programmed in C with supercomputer-class compiler support for automatic vectorization, multithreading, and DSP semantic analysis.

关键词： Convergence hardware Digital signal processing Computer architecture Communication system control Java Multimedia communication Multimedia systems Video signal processing Wireless communication

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Satisfying real-time constraints with custom instructions

Satisfying real-time constraints with custom instructions

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Tulika Mitra Pan Yu School of Computing National University of Singapore Singapore

Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average).

关键词： Real time systems Embedded system Frequency Computer aided instruction Permission Processor scheduling Clocks Timing Integer linear programming Algorithm design and analysis

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A design flow for an H.264 embedded video encoder

A design flow for an H.264 embedded video encoder

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ITI international conference on Information and Communications Technology (ICICT)

作者： I. Amer W. Badawy G. Jullien Advanced Technology Information Processing Systems ATIPS Calgary AB Canada

hardware/software codesign is a rapidly-growing research area branching from hardware synthesis. The purpose of codesign is to facilitate the design of small embedded systems, that is, those consisting of a microprocessor, for which software is required, in addition to one or more semi-custom ASICs or FPGAs. In this paper, a design flow of an H.264 HW/SW digital video encoder is introduced. A design example of a hardware 4times4 DCT-like transform and quantization block integrated with the H.264 software reference model is described

关键词： hardware Quantization Video coding Embedded system Video compression software performance Embedded software Application software Robustness MPEG 4 Standard

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High-level synthesis for large bit-width multipliers on FPGAs: a case study

High-level synthesis for large bit-width multipliers on FPGA...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： James P. Davis Duncan A. Buell Siddhaveerasharan Devarkal Gang Quan Department of Computer Science and Engineering University of South Carolina Columbia SC USA

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource cost-effectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform.

关键词： High level synthesis Field programmable gate arrays Elliptic curve cryptography Error correction Circuit noise Circuit synthesis Network synthesis Throughput Analytical models Timing

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A cycle-accurate compilation algorithm for custom pipelined datapaths

A cycle-accurate compilation algorithm for custom pipelined ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Daniel Gajski Mehrdad Reshadi Center for Embedded Computer Systems CECS University of California Irvine CA USA

Traditional high level synthesis (HLS) techniques generate a datapath and controller for a given behavioral description. The growing wiring cost and delay of today technologies require aggressive optimizations, such as interconnect pipelining, that cannot be done after generating the datapath and without invalidating the schedule. On the other hand, the increasing manufacturing complexities demand approaches that favor design for manufacturability (DFM).To address these problems we propose an approach in which the datapath of the architecture is fully allocated before scheduling and binding. We compile a C program directly to the datapath and generate the controller. We can support the entire ANSI C syntax because the datapath can be as complex as the datapath of a processor. Since there is no instruction abstraction in this architecture we call it No-Instruction-Set-Computer (NISC). As the first step towards realization of a NISC-based design flow, we present an algorithm that maps an application on a given datapath by performing scheduling and binding simultaneously. With this algorithm, we achieved up to 70% speedup on a NISC with a datapath similar to that of MIPS, compared to a MIPS gcc compiler. It also efficiently handles different datapath features such as pipelining, forwarding and multi-cycle units.

关键词： Job shop scheduling High level synthesis Pipeline processing Manufacturing Processor scheduling Wiring Cost function Delay Algorithm design and analysis Scheduling algorithm

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Memory access optimizations in instruction-set simulators

Memory access optimizations in instruction-set simulators

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Prabhat Mishra Mehrdad Reshadi Center for Embedded Computer Systems (CECS) University of California Irvine Irvine CA USA Computer and Information Science and Engineering University of Florida Gainesville FL USA

Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simulators are widely used in embedded systems design. One of the key performance bottlenecks in interpretive simulation is the instruction and data memory access translation between host and target machines. The simulators must maintain and update the status of the simulated processor including memory and register values. A major challenge in the simulation is to efficiently map the target address space to the host address space. This paper presents two optimization techniques that aggressively utilize the spatial locality of the instruction and data accesses in interpretive simulation: signature based address mapping for optimizing general memory accesses; and incremental instruction fetch for optimizing instruction accesses. To demonstrate the utility of this approach we applied these techniques on SimpleScalar simulator, and obtained up to 30% performance improvement. Our techniques complement the recently proposed optimizations (JIT-CCS [1] and IS-CS [2]) and further improve the performance (up to 89%) on ARM7 and Sparc processors.

关键词： Decoding Computational modeling Runtime Computer aided instruction Embedded computing Embedded system Permission Computer simulation Information science Process design

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An efficient direct mapped instruction cache for application-specific embedded systems

An efficient direct mapped instruction cache for application...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chuanjun Zhang Computer Science and Electrical Engineering Department University of Missouri Kansas City Kansas City MO USA

Caches may consume half of a microprocessor's total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing cache power consumption and reducing cache misses are important to reduce total energy consumption of embedded systems. Direct mapped caches consume much less power than that of same sized set associative caches but with a poor hit rate on average. Through experiments, we observe that memory space of direct mapped instruction caches is not used efficiently in most embedded applications. We design an efficient cache - a configurable instruction cache that can be tuned to utilize the cache sets efficiently for a particular application such that cache memory is exploited more efficiently by index remapping. Experiments on 11 benchmarks drawn from Mediabench show that the efficient cache achieves almost the same miss rate as a conventional two-way set associative cache on average and with total memory-access energy savings of 30% compared with a conventional two-way set associative cache.

关键词： Embedded system Energy consumption Delta modulation Cache memory Algorithm design and analysis Cities and towns Computer science Clocks Frequency Application specific processors

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Enhancing security through hardware-assisted run-time validation of program data properties

Enhancing security through hardware-assisted run-time valida...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Anand Raghunathan Niraj K. Jha Srivaths Ravi Divya Arora Department of Electrical Engineering Princeton University Princeton NJ USA NEC Laboratories of America Inc. Princeton NJ USA

The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This is particularly relevant in the embedded domain, where the security solution should be customized to the needs of the target system, while considering other design objectives such as cost, performance, and power. Due to the increasing complexity and shrinking design cycles of embedded software, most embedded systems present a host of software vulnerabilities that can be exploited by security attacks. Many attacks are initiated by causing a violation in the properties of data ( e.g., integrity, privacy, access control rules, etc.) associated with a "trusted" program that is executing on the system, leading to a range of undesirable *** this work, we develop a general framework that provides security assurance against a wide class of security attacks. Our work is based on the observation that a program's permissible behaviorwith respect to data accesses can be characterized by certain properties. We present a hardware/software approach wherein such properties can be encoded as data attributes and enforced as security policies during program execution. These policies may be application-specific (e.g., access control for certain data structures), compiler-generated (e.g., enforcing that variables are accessed only within their scope), or universally applicable to all programs (e.g., disallowing writes to unallocated memory). We show how an embedded system architecture can support such policies by (i) enhancing the memory hierarchy to represent the attributes of each datum as security tags that are linked to it through its lifetime, and (ii) adding a configurable hardware checker that interprets the semantics of the tags and enforces the desired security policies. We evaluated the effectiveness of the proposed architecture in enforcing various security policies for several embedded benchma

关键词： Data security Runtime Information security Power system security Embedded software Embedded system Access control hardware Costs Data privacy

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Designing real-time H.264 decoders with dataflow architectures

Designing real-time H.264 decoders with dataflow architectur...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Suleyman Sair Youngsoo Kim Department of Electrical and Computer Engineering NC State University USA

High performance microprocessors are designed with general-purpose applications in mind. When it comes to embedded applications, these architectures typically perform control-intensive tasks in a system-on-Chip (SoC) design. But they are significantly inefficient for data-intensive tasks such as video encoding/decoding. Although configurable processors fill this gap by complementing the existing functional units with instruction extensions, their performance lags behind the needs of real-time embedded tasks. In this paper, we evaluate the performance potential of a dataflow processor for H.264 video decoding. We first profile the H.264 application to capture the amount of data traffic among modules. We use this information to guide the placement of H.264 modules in the WaveScalar dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in the dataflow architecture. In addition to outperforming contemporary embedded and customized processors, our simulated annealing guided design shows a speedup of 13% in execution time over the original WaveScalar architecture. With our dataflow design methodology, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time.

关键词： Decoding Computer architecture Design methodology Application software Acceleration Encoding Simulated annealing Permission Microprocessors Control systems

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