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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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High-level synthesis for large bit-width multipliers on FPGAs: a case study 05

High-level synthesis for large bit-width multipliers on FPGA...

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Gang Quan James P. Davis Siddhaveerasharan Devarkal Duncan A. Buell University of South Carolina Columbia SC

ISBN: (纸本)9781595931610

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource cost-effectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform.

关键词： reconfigurable computing large-scale integer multipliers FPGA devices high level synthesis design exploration

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Model driven engineering for SoC co-design

Model driven engineering for SoC co-design

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Annual IEEE Northeast Workshop on Circuits and systems (NEWCAS)

作者： J. Dekeyser P. Boulet P. Marquet S. Meftali Laboratoire dInformatique Fondamentale de Lille Université des Sciences et Technologies de Lille Villeneuve d'Ascq France

SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the evolution of the technologies, the best one is the one to come. Evolution of an embedded system both hardware and software, is not simple. The business logic has to be kept and the technical aspect has to be thrown. To improve the permanence of system on chip we have to abstract from the technical concerns. Model driven engineering (MDE) proposes a separation of concerns: application and technical concerns. The use of a modeling standard can capitalize system descriptions and improve system evolution and integration. A particular aspect of MDE concerns model transformations and code generation. At this level, the basic model driven architecture pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models (PSMs). By defining different PIM and PSM dedicated to embedded systems, we show the benefits of using the MDE approach in system on chip codesign. From UML 2.0 profiles to systemC or VHDL codes, the same model transformation engine is used with different rules expressed in XML.

关键词： Model driven engineering Embedded system system-on-a-chip hardware Embedded software Logic Application software Unified modeling language Engines XML

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Blue matter on blue gene/L: massively parallel computation for biomolecular simulation 05

Blue matter on blue gene/L: massively parallel computation f...

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proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis

作者： Robert S. Germain Blake Fitch Aleksandr Rayshubskiy Maria Eleftheriou Michael C. Pitman Frank Suits Mark Giampapa T.J. Christopher Ward IBM Thomas J. Watson Research Center Yorktown Heights NY IBM Hursley Park Hursley UK

ISBN: (纸本)9781595931610

This paper provides an overview of the Blue Matter application development effort within the Blue Gene project that supports our scientific simulation efforts in the areas of protein folding and membrane-protein systems. The design philosophy of the Blue Gene/L architecture relies on large numbers of power efficient nodes (whose technology is derived from the world of embedded microprocessors) to enable packing of many such nodes into a small volume to achieve high performance. In order for an application to exploit the potential of this architecture, the application must scale well to large node counts. Because the scientific goals of the project entail simulating very long time-scales, up to microseconds, strong scaling of a fixed size problem to these large node counts is a requirement. In pursuit of this objective we have considered a variety of parallel decompositions and explored ways to exploit and map algorithms onto the two primary high performance interconnects provided by the Blue Gene architecture, the 3D-torus network and the collective network. Our current version of the application continues to speed up through 4096 nodes and is being used for studies of a protein/lipid system (for which some results have already been published) and for protein folding/unfolding simulations.

关键词： physical design microfluidics biochip synthesis

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A flow-based network monitoring system used for CSCW in design

A flow-based network monitoring system used for CSCW in desi...

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international conference on Computer Supported Cooperative Work in Design

作者： Bo Yang Yi Li Yuehui Chen Runzhang Yuan State Key Laboratory of Advanced Technology for Materials Synthesis and Processing Wuhan University of Science and Engineering China School of Information Science and Technology Jinan University China

ISBN: (纸本)184000025

Technology trends in today's cooperative design environments are making it more and more important to monitor the network performance and ensure the network security. This paper describes the design and implementation of a distributed network traffic monitoring system based on embedded NetFlow hardware and software engines. The system architecture and design principles were introduced in the paper, some discussions were also presented about the NetFlow-based network monitoring technologies. The system had been successfully used to monitor highspeed campus networks at full wire speed without packet sampling in scenarios where commercial NetFlow collectors could not be used due to their limitations. Results show that this is an effective mechanism to identify, diagnose, and determine controls for network activities in CSCW environments and other network-based applications.

关键词： Monitoring Intelligent networks Telecommunication traffic Switches Materials science and technology Sampling methods Probes Protocols Network synthesis Information science

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Dynamic configuration of dataflow graph topology for DSP system design [video encoder example]

Dynamic configuration of dataflow graph topology for DSP sys...

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Dong-Ik Ko S.S. Bhattacharyya Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies University of Maryland College Park USA

Dataflow is widely used for designing DSP applications. Despite its intrinsic advantages, one weak point is its difficulty in flexible expression of applications with data dependent change in execution structure. This paper suggests an approach to providing dynamically configured dataflow graph topologies using a new modeling and synthesis technique called DGT (dynamic graph topology). DGT builds on PSDF semantics (B. Bhattacharya et al, IEEE Tran. on Sig. Proc., vol.49(10), p.2408-2421, 2001). All possible graph topologies for a given graph are obtained at compile time and the corresponding graph based on parameters and data is dynamically set up in an efficient manner at runtime before the invocation of the associated graph. systematic methods for reducing code and buffer size are applied based on characteristics of each configured graph. We have compared DGT against conventional modeling approaches through a detailed case study of an MPEG 2 video encoder system, and our experiments demonstrate the efficiency of the DGT approach.

关键词： Topology Digital signal processing Application software Runtime Data structures Boolean functions hardware Educational institutions Upper bound Equations

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Adaptive streaming panoramic video for image based rendering system

Adaptive streaming panoramic video for image based rendering...

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IEEE international conference on Networking, Sensing and Control

作者： Yu Lei Xiaolin Zheng Zhongding Jiang D. Chen School of Computer Science Zhejiang University China School of Software Fudan University China

In this paper, we present an adaptive panoramic video streaming scheme for distributed image based rendering (IBR) systems. Real-time rendering of complex 3D scene on mobile devices is a challenging task. The main reason is that mobile devices have limited computational capabilities and are lack of powerful 3D graphics hardware support. In such systems, server should take most of the computing job and than transmit the required image segments to client. So the efficient network transmission is vital for client to smoothly synthesize attractive 3D scenes. The proposed streaming scheme fulfils this task by probing the mobile network's status and then effective adjust the sending data to avoid network congestion and jitter. Pre-fetching and cache management are also considered for efficient memory usage and reducing transmission requests. With the help of this scheme, we implemented an interactive distributed 3D walk through system on both mobile devices and desktop computers. Experimental results show that the adaptive panoramic video streaming scheme is useful for the distributed IBR systems.

关键词： Streaming media Rendering (computer graphics) Layout Mobile computing Memory management Graphics hardware Network servers Image segmentation Network synthesis

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First IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2000

First IEEE/ACM/IFIP International Conference on Hardware/Sof...

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First IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

The proceedings contains 38 papers from the First IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003. The topics discussed include: RTOS scheduling in transaction level models;hardware support for real-time operating systems;a fast parallel Reed-Solomon decoder on a reconfigurable architecture;a low power scheduler using game theory;programmers' views of SoCs;and verification of design decisions in ForSyDe.

关键词： Computer operating systems

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hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

Hardware synthesis from coarse-grained dataflow specificatio...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Jung, H Ha, S Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151744 South Korea

ISBN: (纸本)1581139373

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

关键词： HW/SW codesign system level design dataflow graph(DFG) VHDL autonomic hardware synthesis

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RTOS-centric hardware/software cosimulator for embedded system design

RTOS-centric hardware/software cosimulator for embedded syst...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Honda, S Wakabayashi, T Tomiyama, H Takada, H Toyohashi Univ Technol Dept Informat & Comp Sci Toyohashi Aichi 4418580 Japan

ISBN: (纸本)1581139373

This paper presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

关键词： RTOS cosimulation embedded systems

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Current flattening in software and hardware for security applications

Current flattening in software and hardware for security app...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Muresan, R Gebotys, C Univ Guelph Guelph ON N1G 2W1 Canada

ISBN: (纸本)1581139373

This paper presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation dependency on data and program) compromise the security of the system. The technique flattens the current internally by exploiting current consumption differences at the instruction level. Code transformations supporting current variation reductions due to program dependencies are presented. Also, a new real-time hardware architecture capable of reducing the current to data and program dependencies is proposed. Measured and simulated current waveforms of cryptographic software are presented in support of these techniques.

关键词： current flattening power analysis attacks hardware architecture

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