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system-on-chip validation using UML and CWL

System-on-chip validation using UML and CWL

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Zhu, Q Oishi, R Hasegawa, T Nakata, T Fujitsu Labs Ltd Nakahara Ku Kawasaki Kanagawa 2118588 Japan

ISBN: (纸本)1581139373

In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design. The consistency and completeness of the specification is validated based on the formal UML model. The implementation is validated by a systematic derivation of test scenarios and specification based coverage metrics from the UML model. The method has been applied to the design of a new media-processing chip for mobile devices. The application of the method shows that it is not only effective for finding logical errors in the implementation, but also eliminates errors due to inconsistency and incompleteness of the specification.

关键词： verification process UML validation and verification specification modeling

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Memory accesses management during high level synthesis

Memory accesses management during high level synthesis

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Corre, G Senn, E Bomel, P Julien, N Martin, E Univ S Brittany LESTER F-56321 Lorient France

ISBN: (纸本)1581139373

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

关键词： memory aware behavioral synthesis

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hardware software codesign of the Xilinx Microkernel

Hardware software codesign of the Xilinx Microkernel

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proceedings of the international conference on Engineering of Reconfigurable systems and Algorithms, ERSA'04

作者： Asokan, Vasanth Mohan, S. Nagarajan, Raj K. Xilinx Inc.

ISBN: (纸本)1932415424

In this paper, we describe work in progress on a methodology for the hardware-software codesign of the Xilinx Micro-Kernel (XMK), leveraging the Xilinx Platform Studio (XPS) [1]. Combined with the Microblaze [2] soft-processor and the XPS system design framework, XMK is an ideal target for hardware acceleration due its modular design and configurability. Our methodology will target FPGA devices for programmable processor systems and target the fine-grain, yet, efficient hardware-software partitioning that is possible. We present our vision for the entire framework, which can address system level issues as well.

关键词： Computer software

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Using C based logic synthesis to bridge the productivity gap

Using C based logic synthesis to bridge the productivity gap

引用

Asia and South Pacific Design Automation conference

作者： Sullivan, C Wilson, A Chappell, S Celoxica Ltd. United Kingdom

ISBN: (纸本)0780381750

Digital circuits from software designs and formal executable specifications can be automatically synthesized using hardware compilation or 'C based logic synthesis'. Designs can be verified using that same formal specification and coupled with the increasing deployment of higher-level C based languages and IP reuse in hardware design and system codesign, C based logic synthesis is enabling new methodologies and levels of designer productivity. In this paper we discuss the rationale for such a synthesis approach, the required semantics and compilation technology and offer a contrast with RTL synthesis. Design examples are used to provide case studies of practical experience.

关键词： Computer software

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Cellular handset technology system requirements and integration trends

Cellular handset technology system requirements and integrat...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Mattisson, S Ericsson Mobile Platforms AB Strateg Prod Management Analog Syst Design SE-22183 Lund Sweden

ISBN: (纸本)1581139373

In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time have been reduced by more than a factor of ten. These factors have been critical for the success story of the mobile phone. The technical aspects behind the rapid handset evolution are discussed. In particular, what advances in the radio architecture, for example the zero-IF GSM receiver, the baseband (CMOS) technology, and the radio system design areas have meant for the reduction of size, weight, cost, and power consumption is discussed. Future challenges, like SW-DSP-digital-RF partitioning, linear multi-mode modulation with high linearity requirements, digital leakage issues, and power consumption limitations in multimedia handsets are discussed with future generation handsets in mind.

关键词： Cellular telephone systems

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Future challenges in embedded systems 04

Future challenges in embedded systems

引用

Second IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

作者： Cuomo, Andrea Advanced System Technology ST Microelectronics

ISBN: (纸本)1581139373

Embedded systems will play a key role to drive the technological evolution in the next 20 years. Their evolution will further accelerate with the diffusion of the novel technologies that will deeply change our scenario, among which we can mention nanotechnologies, bioelectronics, and photonics. The central role of embedded systems in the economy will grow stronger and stronger: the starting point is the convergence between storage, security, video, audio, mobility and connectivity. systems are converging and ICs are more and more converging with systems: this poses a number of challenges for designers and technologists. A key issue is the definition of the right methodologies to translate system knowledge and competences into complex embedded systems, taking into account many system requirements and constraints. The key factor to win this challenge is to build the right culture. This means to be able to build the right environment to exploit existing design, architectural and technological solutions, and to favor the transfer of knowledge from one application field into another.

关键词： Embedded systems

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High level synthesis methodology from C to FPGA used for a network protocol communication.

High level synthesis methodology from C to FPGA used for a n...

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15th IEEE international Workshop on Rapid system Prototyping

作者： Diaby, M Tuna, M Desbarbieux, JL Wajsburt, F Univ Paris 06 LIP6 Lab Dept ASIM F-75252 Paris 05 France

ISBN: (纸本)0769521592

This paper presents a "Kahn Process Network" methodology based on the DISYDENT platform (DIgital system Design ENvironmenT). The system is described by a set of communicating Kahn processes. This processes are C POSIX threads representing both software and hardware tasks. Each thread communicates with the others using channel-read / channel-write primitives. Thus, the system can be validated efficiently and quickly by software. system's realization consists of synthesizing hardware tasks to RTL-VHDL language. This step is automated from C task to FPGA mapping. This paper shows the method's effectiveness through the realization of a network controller on FPGA enabling communication between two Linux stations.

关键词： high level synthesis KPN hardware/software codesign FPGA code generator VHDL

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Efficient exploration of on-chip bus architectures and memory allocation

Efficient exploration of on-chip bus architectures and memor...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Kim, S Im, C Ha, SH Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151744 South Korea

ISBN: (纸本)1581139373

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies trace-driven simulation technique to the reduced set of design candidates for accurate performance estimation. Since local memory traffic as well as shared memory traffic are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology are validated by two real-life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

关键词： system-on-a-chip design space exploration communication architecture optimization memory allocation

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Memory system design space exploration for low-power, real-time speech recognition

Memory system design space exploration for low-power, real-t...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Krishna, R Mahlke, S Austin, T Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)1581139373

The recent proliferation of computing technology has generated new interest natural I/O interface technologies such as speech recognition. Unfortunately, the computational and memory demands of such applications currently prohibit their use on low-power portable devices in anything more than their simplest forms. Previous work has demonstrated that the thread level concurrency inherent in this application domain can be used to dramatically improve performance with minimal impact on overall system energy consumption, but that such benefits are severely constrained by memory system bandwidth. This work presents a design space exploration of potential memory system architectures. A range of low-power memory organizations are considered, from conventional caching to more advanced system-on-chip implementations. We find that, given architectures able to exploit concurrency in this domain, large L2 based cache hierarchies and high bandwidth memory systems employing data stream partitioning and on-chip embedded DRAM and ROM technologies can provide much of the performance of idealized memory systems without violating the power constraints of the low-power domain.

关键词： performance design

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Fast co-simulation of transformative systems with OS support on SMP computer

Fast co-simulation of transformative systems with OS support...

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2nd international conference on hardware/software codesign and systems synthesis

作者： He, ZT Mok, A Univ Texas Dept Elect & Comp Engn Austin TX 78712 USA

ISBN: (纸本)1581139373

Transformative applications are a class of dataflow computation characterized by iterative behavior. The problem of partitioning a transformative application specification to a set of available hardware (HW) and software (SW) processing elements (PEs) and derivation of a job execution order (scheduling) on them has been quite well studied, but the problem of obtaining fast simulation of these applications poses different constraints. In this paper, we propose an efficient framework for a symmetric multi-processor (SMP) simulation host to achieve fast HW/SW co-simulation for transformative applications, given the partition solutions and the derived schedulers. The framework overcomes the limitations in existing Linux SMP kernel and requires only a reasonable amount of modifications to it. We also present a heuristic algorithm which effectively assigns simulation tasks to the processors on the simulation host, considering both average job simulation time on each processor and other simulation overhead. Our experiments show that the algorithm is able to find satisfactory suboptimal solutions with very little computation time. Based on the task assignment solution, the simulation time can be reduced by 25% to 50% from the obvious but naive approach.

关键词： HW/SW co-simulation transformative system task assignment SMP

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