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检索条件"任意字段=Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis"

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A platform-based SoC hardware/software co-design environment

A platform-based SoC hardware/software co-design environment

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8th international conference on Computer Supported Cooperative Work in Design

作者： Xiong, ZH Li, SK Chen, JH Wang, DW Natl Univ Def Technol Sch Comp Sci Changsha 410073 Peoples R China

ISBN: (纸本)0780379411

This paper presents a Platform-based SoC hardware/software co-design environment named HSCDE. It introduces the overall structure of HSCDE, describes the Platform-based SoC system modeling technology, ant algorithm based hardware/software partitioning technology and Hierarchical Directed Acyclic Graph based performance constraint assignment technology. HSCDE supports Platform-based SoC hardware/software co-design methodology. It supports almost all the design phases from SoC system modeling to RTL level SoC system. It divides SoC hardware/software co-design into system modeling level (level 1), virtual components level (level 2) and real components level (level 3), and it performs the 2 mappings among the 3 design levels by Design Planning (mapping 1) and Virtual-Real synthesis (mapping 2). We have done SoC system design for MP3 player SoC, MEPG2 player SoC and CDMA wireless communication SoC in HSCDE environment. Results show that HSCDE effectively supports Platform-based SoC hardware/software co-design methodology;it enhanced system reuse of existing SoC design. Statistics indicate an average of 10%similar to25% revisions on platform templates for a new SoC design, and we achieved platform template reuse ratio by 75%similar to90%.

关键词： Microprocessor chips

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international conference on hardware/software codesign and systems synthesis (IEEE Cat. No.04TH8785)

International Conference on Hardware/Software Codesign and S...

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international conference on hardware/software codesign and system synthesis (CODES)

The following topics are dealt with: organic computing; design techniques for application specific processors; advances in software and hardware synthesis techniques for DSP applications; multiprocessor SoC design strategies and programming models; energy-aware compiling and scheduling; system-level design space exploration for hardware-software partitioning and platform instantiation; estimation and design techniques for energy-efficient memory systems; advances in hardware/software co-simulation techniques; NoC design and optimisation; software and hardware techniques for performance optimisation of embedded applications; techniques for security and reliability enhancement in embedded systems; and on-chip communication architecture analysis and optimisation.

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systemoprh: Dynamic/online/adaptive system-level optimization for SoC

SysteMoprh: Dynamic/online/adaptive system-level optimizatio...

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7th international conference on High Performance Computing and Grid in Asia Pacific Region (HPCAsia 2004)

作者： Yoshimatsu, N Yoshida, M Soga, T Shuto, M Tanoue, Y Fujii, Y Eshima, K Hayashida, T Murakami, K Fukuoka Ind Sci & Technol Fdn Fukuoka Japan

ISBN: (纸本)076952138X

This paper describes systemorph, a feedback directed dynamic, online and adaptive hardware/instruction set architecture (ISA)/software co-optimization technology. The technology enables to optimize performance, power and consumption energy for a system dynamically. We describe systemorphs elemental technologies those are an online profiling, a dynamic adaptive optimization and a smart hardware. Functionality Morphing is one of the systemorph implementations for a system which consists of processor and reconfigurable logic. It reconfigures hardware dynamically then rewrites software to utilize the reconfigured hardware online. We demonstrated the systemorph on a reconfigurable processor by implementing Functionality Morphing. Online profiling, online synthesis, and binary rewriting are implemented and verified on the prototypal system. Then we propose a processor suitable implementing systemorph using a VLIW execution unit.

关键词： Very long instruction word architecture

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Dynamic reconfiguration of distributed arithmetic controllers: Design space exploration and trade-off analysis

Dynamic reconfiguration of distributed arithmetic controller...

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proceedings - 18th international Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

作者： Danne, Klaus Bobda, Christophe University of Paderborn Heinz Nixdorf Institute Fürstenallee 11 33102 Paderborn Germany University of Erlangen-Nuremberg Hardware/Software Codesign Institute Am Weichselgarten 3 91058 Erlangen Germany

ISBN: (纸本)0769521320

This work explores various solutions to implement an application using runtime reconfigurable field programmable gate arrays (FPGA). The example is a mechatronic control system which has to adapt its behavior from time to time. Our model is a task-graph where every task is associated with an hardware module characterized by its required FPGA resource and its execution time. We propose various mappings of the tasks onto the FPGA. For the implementation of the tasks themselves the computation technique known as distributed arithmetic is used. We achieve numerous alternatives with different resource consumptions and execution times for every task. We estimate these characteristics and compare them to synthesis results. The received values are used to get the characteristics of the over-all system. The results show that the optimal mapping depends on the application timing constrains, on the complexity of the tasks as well as on the reconfiguration speed of the used FPGA1.

关键词： Programmable logic controllers

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Cosynthesis of multiprocessor architectures with high availability

Cosynthesis of multiprocessor architectures with high availa...

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17th international conference on VLSI Design

作者： Chakraverty, S Netaji Subhas Inst Technol New Delhi 110045 India

ISBN: (纸本)0769520723

The co-synthesis of hardware-software systems for distributed and/or embedded applications has been studied extensively in the recent past, in combination with various qualitative objectives. However, the issues related to design exploration for gracefully degrading systems with the specific objective of achieving the desired levels of availability need to be addressed systematically. In this paper, we propose a cosynthesis mechanism for generating gracefully degrading multiprocessor architectures which fulfill the dual objectives of achieving real-time performance as well as ensuring high levels of system availability as defined by the user's availability expectations under different states of functionality. A rule-based model for incorporating the user's availability requirements and evaluating the system availability is coupled with a stochastic scheduling technique and a genetic algorithm (CA) to optimize the resource selections, task allocations and task schedules. Results show that it is possible to obtain a range of near-optimal solutions, offering tradeoffs between performance and availability benefits at different costs.

关键词： Computer hardware

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Current flattening in software and hardware for security applications 04

Current flattening in software and hardware for security app...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： R. Muresan C. Gebotys University of Guelph Guelph ONT Canada University of Waterloo Waterloo ONT Canada

ISBN: (纸本)9781581139372

This work presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation dependency on data and program) compromise the security of the system. The technique flattens the current internally by exploiting current consumption differences at the instruction level. Code transformations supporting current variation reductions due to program dependencies are presented. Also, real-time hardware architecture capable of reducing the current to data and program dependencies is proposed. Measured and simulated current waveforms of cryptographic software are presented in support of these techniques.

关键词： hardware Application software Energy consumption Elliptic curve cryptography Public key cryptography Timing Data security Protocols Power system security Information analysis

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Embedded systems education: How to teach the required skills?

Embedded systems education: How to teach the required skills...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： P. Marwedel D. Gajski E. De Kock H. De Man M. Sami I. Soderquist University of Dortmund Germany University of California Irvine USA Phillips Netherlands KU Leuven Belgium Saab Sweden

The goal of this panel is to contrast existing approaches to embedded system education with the needs in industry. Embedded system design is currently not yet well represented in academic programs. The general trend toward embedded systems requires a drastic change of that situation. This panel aims at starting a discussion on how current curricula should he revised in order to take the requirements of modem technologies into account.

关键词： Embedded system Educational programs hardware Application software Modems Communication system software Multimedia systems Streaming media software algorithms Algorithm design and analysis

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RTOS-centric hardware/software cosimulator for embedded system design 04

RTOS-centric hardware/software cosimulator for embedded syst...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Honda T. Wakabayashi H. Tomiyama H. Takada Department of Information and Computer Science Toyohashi University of Technology Toyohashi Japan Graduate School of Information Science University of Nagoya Nagoya Japan

ISBN: (纸本)9781581139372

This work presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

关键词： Embedded software Embedded system Computational modeling Application software hardware design languages Permission Computer science Information science Computer simulation Computer industry

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hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis 04

Hardware synthesis from coarse-grained dataflow specificatio...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hyunuk Jung Soonhoi Ha School of Electrical Engineering and Computer Science Seoul National University Seoul South Korea

ISBN: (纸本)1581139373

This work concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

关键词： hardware system-level design Flow graphs Design methodology Logic Permission Computer science Data flow computing Finite impulse response filter Discrete cosine transforms

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Integrating assertion-based verification into system-level synthesis methodology

Integrating assertion-based verification into system-level s...

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16th international conference on Microelectronics, ICM 2004

作者： Hessabi, Shaahin Gharehbaghi, Amir Masoud Yaran, Benyamin Hamdin Goudarzi, Maziar Department of Computer Engineering Sharif University of Technology

In this paper we integrate a verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification after system synthesis. We have defined a set of system-level assertions. These assertions are automatically converted to monitor hardware or monitor software during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertion, and hence, can be used to verify the system after HW/SW synthesis. This way, not only system-level assertions are reused in lower-levels of abstraction, but also run-time verification of system is provided. In this paper, we show the system-level assertions and their synthesis method in our object-oriented system-level synthesis methodology. © 2004 IEEE.

关键词： systems analysis

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