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检索条件"任意字段=Proceedings of the International Workshop on Algorithms and Parallel VSLI Architectures"

共 181 条记录，以下是1-10 订阅

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proceedings of international workshop on OpenCL and SYCL, IWOCL 2024

Proceedings of International Workshop on OpenCL and SYCL, IW...

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12th international workshop on OpenCL and SYCL, IWOCL 2024

ISBN: (纸本)9798400717901

The proceedings contain 22 papers. The topics discuss include: towards efficient OpenCL pipe specification for hardware accelerators;SimSYCL: a SYCL implementation targeting development, debugging, simulation and conformance;experiences with implementing Kokkos’ SYCL backend;optimization and evaluation of breadth first search with oneAPI/SYCL on Intel FPGAs: from describing algorithms to describing architectures;improving performance portability of the procedurally generated high energy physics event generator MadGraph using SYCL;unlocking performance portability on LUMI-G supercomputer: a virtual screening case study;evaluation of SYCL’s different data parallel kernels;smoothing the migration from CUDA to SYCL: SYCLomatic utility features;and optimization of fast Fourier transform (FFT) for Qualcomm Adreno graphics processing unit.

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Modeling TCP Performance using Graph Neural Networks 1

Modeling TCP Performance using Graph Neural Networks

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1st international workshop on Graph Neural Networking (GNNet)

作者： Jaeger, Benedikt Helm, Max Schwegmann, Lars Carle, Georg Tech Univ Munich Chair Network Architectures & Serv Munich Germany

ISBN: (纸本)9781450399333

TCP throughput and RTT prediction are essential to model TCP behavior and optimize network configurations. Flows adapt their sending rate to network parameters like link capacity or buffer size and interact with parallel flows. Especially the elastic behavior of TCP congestion control can vary, even when only slight changes in the network occur. Thus, existing analytical models for TCP behavior reach their limits due to the number and complexity of different algorithms. Machine learning approaches, in contrast, are often fixed to specific network topologies. This paper presents a TCP bandwidth and RTT prediction approach that can handle different algorithms and topologies. For this, we utilize Gated Graph Neural Networks and simulated network traffic. We evaluate different encodings of the input data into graphs and how network size, number of flows, and TCP algorithms influence prediction accuracy. Additionally, we quantify the impact of different input features on our models. We show that Graph Neural Networks can be used to model TCP behavior. The resulting models can predict RTT with a median relative error of 2.29 % and throughput with an error of 13.31 %.

关键词： TCP modeling congestion control throughput round-trip time graph neural networks

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Domain Decomposition Preconditioners for Unstructured Network Problems in parallel Vector architectures 21

Domain Decomposition Preconditioners for Unstructured Networ...

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50th international Conference on parallel Processing (ICPP)

作者： Maldonado, Daniel Adrian Schanen, Michel Pacaud, Francois Anitescu, Mihai Argonne Natl Lab Lemont IL 60439 USA

ISBN: (纸本)9781450384414

In this paper we present our experience implementing domain decomposition preconditioners on vector architectures. In particular, we will focus on the solution of unstructured network equations arising from electrical power systems by preconditioning iterative algorithms with the Additive Schwarz Method (ASM). The implementation will be carried out using the Julia programming language, which allows for easy prototyping and interfacing with GPU architectures thanks to its multiple dispatch features. In our experiments, we will show the trade-off between device throughput and convergence of the iterative algorithm as the size of the domain varies, and determine optimal fronts of computational performance.

关键词： Iterative methods

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Scalable parallel algorithm for fast computation of Transitive Closure of Graphs on Shared Memory architectures 6

Scalable parallel algorithm for fast computation of Transiti...

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IEEE/ACM 6th international workshop on Extreme Scale Programming Models and Middleware (ESPM2)

作者： Patel, Sarthak Dave, Bhrugu Kumbhani, Smit Desai, Mihir Kumar, Sidharth Chaudhury, Bhaskar DA IICT Grp Computat Sci & HPC Gandhinagar India Univ Alabama Birmingham Dept Comp Sci Birmingham AL 35294 USA

ISBN: (纸本)9781665411400

We present a scalable algorithm that computes the transitive closure of a graph on shared memory architectures using the OpenMP API in C++. Two different parallelization strategies have been presented and the performance of the two algorithms has been compared for several data-sets of varying sizes. We demonstrate the scalability of the best parallel implementation up to 176 threads on a shared memory architecture, by producing a graph with more than 3.82 trillion edges. To the best of our knowledge, this is the first implementation that has computed the transitive closure of such a large graph on a shared memory system. Optimization strategies for better cache utilization for large data-sets have been discussed. The important issue of load balancing has been analyzed and its mitigation using the optimal OpenMP scheduling clause has been discussed in detail.

关键词： Graph algorithms OpenMP Transitive Closure Scalability Shared memory

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proceedings of PMBS 2022: Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, Held in conjunction with SC 2022: The international Conference for High Performance Computing, Networking, Storage and Analysis

Proceedings of PMBS 2022: Performance Modeling, Benchmarking...

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13th IEEE/ACM international workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, PMBS 2022

ISBN: (纸本)9781665451857

The proceedings contain 14 papers. The topics discussed include: ML-based performance portability for time-dependent density functional theory in HPC environments;a comprehensive evaluation of novel ai accelerators for deep learning workloads;frontier vs the exascale report: why so long? and are we really there yet?;evaluating ISO C++ parallel algorithms on heterogeneous HPC systems;going green: optimizing GPUs for energy efficiency through model-steered auto-tuning;performance analysis with unified hardware counter metrics;a methodology for evaluating tightly-integrated and disaggregated accelerated architectures;WfBench: automated generation of scientific workflow benchmarks;high-performance GMRES multi-precision benchmark: design, performance, and challenges;and an initial evaluation of arm’s scalable matrix extension.

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Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM 21

Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM

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50th international Conference on parallel Processing (ICPP)

作者： Ghanim, Fady Elwasif, Wael R. Bernholdt, David E. Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9781450384414

The parallel Random Access Machines (PRAM) abstraction is the simplest and most elegant algorithmic model for the design and analysis of parallel algorithms. It consists of different models categorized based on the underlying memory access mode used, the most powerful of which is the Concurrent Read Concurrent Write (CRCW) model. A PRAM algorithm describes a series of rounds, each of which consists of a collection of operations that can be executed concurrently within the same time step. However, the lack of support for concurrent memory accesses and the prevalence of asynchronous programming models led to the belief that implementing CRCW PRAM algorithms is unattainable and prompted many to avoid this model except for theoretical studies of optimal performance. In this work, we study the arbitrary and common concurrent writes in the CRCW PRAM model and explore implementation challenges on general-purpose systems. Moreover, we examine current practices for implementing common/arbitrary concurrent writes and propose a new efficient lightweight and thread-safe method to implement concurrent writes through leveraging atomic instructions. To demonstrate the efficacy of our method, we developed OpenMP kernels for classical CRCW PRAM algorithms and provide experimental results and comparisons based on run time performance measured over the x86 multicore architecture. Our results show a performance speedup compared to current practices up to 4.5x across all our benchmarks.

关键词： CRCW PRAM parallel algorithms Arbitrary Concurrent Writes Write-conflict resolution parallel architectures

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parallel SIMD-A Policy Based Solution for Free Speed-Up using C++ Data-parallel Types 6

Parallel SIMD-A Policy Based Solution for Free Speed-Up usin...

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6th international IEEE/ACM workshop on Extreme Scale Programming Models and Middleware, ESPM2 2021

作者： Yadav, Srinivas Gupta, Nikunj Reverdell, Auriane Kaiser, Hartmut Keshav Memorial Institute of Technology Hyderabad India University of Illinois at Urbana-Champaign Illinois United States Swiss National Supercomputing Centre Zurich Switzerland Louisiana State University Center for Computation Technology Baton Rouge United States

ISBN: (纸本)9781665411400

Recent additions to the C++ standard and ongoing standardization efforts aim to add data-parallel types to the C++ standard library. This enables the use of vectorization techniques in existing C++ codes without having to rely on the C++ compiler's abilities to auto-vectorize the code's execution. The integration of the existing parallel algorithms with these new data-parallel types opens up a new way of speeding up existing codes with minimal effort. Today, only very little implementation experience exists for potential data-parallel execution of the standard parallel algorithms. In this paper, we report on experiences and performance analysis results for our implementation of two new data-parallel execution policies usable with HPX's parallel algorithms module: simd and par_simd. We utilize the new experimental implementation of data-parallel types provided by recent versions of the GCC and Clang C++ standard libraries. The benchmark results collected from artificial tests and real-world codes presented in this paper are very promising. Compared to sequenced execution, we report on speed-ups of more than three orders of magnitude when executed using the newly implemented data-parallel execution policy par_simd with HPX's parallel algorithms. We also report that our implementation is performance portable across different compute architectures (x64-Intel and AMD, and Arm), using different vectorization extensions (AVX2, AVX512, and NEON128). © 2021 IEEE.

关键词： parallel algorithms

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proceedings of IA3 2020: 10th workshop on Irregular Applications: architectures and algorithms, Held in conjunction with SC 2020: The international Conference for High Performance Computing, Networking, Storage and Analysis

Proceedings of IA3 2020: 10th Workshop on Irregular Applicat...

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10th workshop on Irregular Applications: architectures and algorithms, IA3 2020

ISBN: (纸本)9780738110905

The proceedings contain 8 papers. The topics discussed include: accelerating domain propagation: an efficient GPU-parallel algorithm over sparse matrices;parallelizing irregular computations for molecular docking;reducing queuing impact in irregular data streaming applications;supporting irregularity in throughput-oriented computing by SIMT-SIMD integration;DistDGL: distributed graph neural network training for billion-scale graphs;labeled triangle indexing for efficiency gains in distributed interactive subgraph search;distributed memory graph coloring algorithms for multiple GPU;and performance evaluation of the vectorizable binary search algorithms on an FPGA platform.

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proceedings of the 11th workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures / 9th workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020

Proceedings of the 11th Workshop on Parallel Programming and...

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11th workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures / 9th workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020

The proceedings contain 5 papers. The topics discussed include: sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system;run-time power modelling in embedded GPUs with dynamic voltage and frequency scaling;fault-tolerant online scheduling algorithms for CubeSats;an OpenMP parallel genetic algorithm for design space exploration of heterogeneous multi-processor embedded systems;and automated precision tuning in activity classification systems: a case study.

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Proceedings of the 11th Workshop on Parallel Programming and...

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8th international Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017

ISBN: (纸本)9781450375450

The proceedings contain 5 papers. The topics discussed include: sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system;run-time power modeling in embedded GPUs with dynamic voltage and frequency scaling;fault-tolerant online scheduling algorithms for CubeSats;an OpenMP parallel genetic algorithm for design space exploration of heterogeneous multi-processor embedded systems;and automated precision tuning in activity classification systems: a case study.

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