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检索条件"任意字段=Proceedings of the International Workshop on Algorithms and Parallel VSLI Architectures"
181 条 记 录,以下是1-10 订阅
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proceedings of international workshop on OpenCL and SYCL, IWOCL 2024
Proceedings of International Workshop on OpenCL and SYCL, IW...
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12th international workshop on OpenCL and SYCL, IWOCL 2024
The proceedings contain 22 papers. The topics discuss include: towards efficient OpenCL pipe specification for hardware accelerators;SimSYCL: a SYCL implementation targeting development, debugging, simulation and conf...
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Modeling TCP Performance using Graph Neural Networks  1
Modeling TCP Performance using Graph Neural Networks
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1st international workshop on Graph Neural Networking (GNNet)
作者: Jaeger, Benedikt Helm, Max Schwegmann, Lars Carle, Georg Tech Univ Munich Chair Network Architectures & Serv Munich Germany
TCP throughput and RTT prediction are essential to model TCP behavior and optimize network configurations. Flows adapt their sending rate to network parameters like link capacity or buffer size and interact with paral... 详细信息
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Domain Decomposition Preconditioners for Unstructured Network Problems in parallel Vector architectures  21
Domain Decomposition Preconditioners for Unstructured Networ...
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50th international Conference on parallel Processing (ICPP)
作者: Maldonado, Daniel Adrian Schanen, Michel Pacaud, Francois Anitescu, Mihai Argonne Natl Lab Lemont IL 60439 USA
In this paper we present our experience implementing domain decomposition preconditioners on vector architectures. In particular, we will focus on the solution of unstructured network equations arising from electrical... 详细信息
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Scalable parallel algorithm for fast computation of Transitive Closure of Graphs on Shared Memory architectures  6
Scalable parallel algorithm for fast computation of Transiti...
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IEEE/ACM 6th international workshop on Extreme Scale Programming Models and Middleware (ESPM2)
作者: Patel, Sarthak Dave, Bhrugu Kumbhani, Smit Desai, Mihir Kumar, Sidharth Chaudhury, Bhaskar DA IICT Grp Computat Sci & HPC Gandhinagar India Univ Alabama Birmingham Dept Comp Sci Birmingham AL 35294 USA
We present a scalable algorithm that computes the transitive closure of a graph on shared memory architectures using the OpenMP API in C++. Two different parallelization strategies have been presented and the performa... 详细信息
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proceedings of PMBS 2022: Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, Held in conjunction with SC 2022: The international Conference for High Performance Computing, Networking, Storage and Analysis
Proceedings of PMBS 2022: Performance Modeling, Benchmarking...
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13th IEEE/ACM international workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems, PMBS 2022
The proceedings contain 14 papers. The topics discussed include: ML-based performance portability for time-dependent density functional theory in HPC environments;a comprehensive evaluation of novel ai accelerators fo...
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Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM  21
Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM
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50th international Conference on parallel Processing (ICPP)
作者: Ghanim, Fady Elwasif, Wael R. Bernholdt, David E. Oak Ridge Natl Lab Oak Ridge TN 37830 USA
The parallel Random Access Machines (PRAM) abstraction is the simplest and most elegant algorithmic model for the design and analysis of parallel algorithms. It consists of different models categorized based on the un... 详细信息
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parallel SIMD-A Policy Based Solution for Free Speed-Up using C++ Data-parallel Types  6
Parallel SIMD-A Policy Based Solution for Free Speed-Up usin...
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6th international IEEE/ACM workshop on Extreme Scale Programming Models and Middleware, ESPM2 2021
作者: Yadav, Srinivas Gupta, Nikunj Reverdell, Auriane Kaiser, Hartmut Keshav Memorial Institute of Technology Hyderabad India University of Illinois at Urbana-Champaign Illinois United States Swiss National Supercomputing Centre Zurich Switzerland Louisiana State University Center for Computation Technology Baton Rouge United States
Recent additions to the C++ standard and ongoing standardization efforts aim to add data-parallel types to the C++ standard library. This enables the use of vectorization techniques in existing C++ codes without havin... 详细信息
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proceedings of IA3 2020: 10th workshop on Irregular Applications: architectures and algorithms, Held in conjunction with SC 2020: The international Conference for High Performance Computing, Networking, Storage and Analysis
Proceedings of IA3 2020: 10th Workshop on Irregular Applicat...
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10th workshop on Irregular Applications: architectures and algorithms, IA3 2020
The proceedings contain 8 papers. The topics discussed include: accelerating domain propagation: an efficient GPU-parallel algorithm over sparse matrices;parallelizing irregular computations for molecular docking;redu...
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proceedings of the 11th workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures / 9th workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020
Proceedings of the 11th Workshop on Parallel Programming and...
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11th workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures / 9th workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020
The proceedings contain 5 papers. The topics discussed include: sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system;run-time power modelling in embedded GPUs with dynamic voltage and fr...
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proceedings of the 11th workshop on parallel Programming and Run-Time Management Techniques for Many-Core architectures / 9th workshop on Design Tools and architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2020
Proceedings of the 11th Workshop on Parallel Programming and...
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8th international Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017
The proceedings contain 5 papers. The topics discussed include: sparse matrix-dense matrix multiplication on heterogeneous CPU+FPGA embedded system;run-time power modeling in embedded GPUs with dynamic voltage and fre...
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