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Embedded Computer Systems: architectures, Modeling, and Simulation - 6th international workshop, SAMOS 2006, proceedings

Embedded Computer Systems: Architectures, Modeling, and Simu...

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6th international workshop on architectures, Modeling, and Simulation, SAMOS 2006

ISBN: (纸本)3540364102

The proceedings contain 48 papers. The topics discussed include: reconfigurable platform for digital convergence terminals;European research in embedded systems;interface overheads in embedded multimedia software;automated distribution of UML 2.0 designed applications to a configurable multiprocessor platform;key research challenges for successfully applying MDD within real-time embedded software development;domain-specific modeling of power aware distributed real-time embedded systems;mining dynamic document spaces with massively parallel embedded processors;designing wireless sensor nodes;design, implementation, and experiment on outdoor deployment of wireless sensor network for environmental monitoring;energy-driven partitioning of signal processing algorithms in sensor networks;security in wireless sensor networks: considerations and experiments;on security of PAN wireless systems;and code size reduction by compiler tuning.

关键词： Computer systems

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A parallel approach to XML parsing 06

A parallel approach to XML parsing

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7th IEEE/ACM international Conference on Grid Computing

作者： Lu, Wei Chiu, Kenneth Pan, Yinfei Indiana Univ Dept Comp Sci 150 S Woodlawn Ave Bloomington IN 47405 USA SUNY Binghamton Dept Comp Sci Binghamton NY 13902 USA

ISBN: (纸本)9781424403431

A language for semi-structured documents, XML has emerged as the core of the web services architecture, and is playing crucial roles in messaging systems, databases, and document processing. However, the processing of XML documents has a reputation for poor performance, and a number of optimizations have been developed to address this performance problem from different perspectives, none of which have been entirely satisfactory. In this paper, we present a seemingly quixotic, but novel approach: parallel XML parsing. parallel XML parsing leverages the growing prevalence of multicore architectures in all sectors of the computer market, and yields significant performance improvements. This paper presents our design and implementation of parallel XML parsing. Our design consists of an initial preparsing phase to determine the structure of the XML document, followed by a full, parallel parse. The results of the preparsing phase are used to help partition the XML document for data parallel processing. Our parallel parsing phase is a modification of the libxml2 [1] XML parser, which shows that our approach applies to real-world, production quality parsers. Our empirical study shows our parallel XML parsing algorithm can improved the XML parsing performance significantly and scales well.

关键词： XML Web services Service oriented architecture Databases Multicore processing Computer architecture Concurrent computing parallel processing Production Partitioning algorithms

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An optimal skew-insensitive join and multi-join algorithm for distributed architectures

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16th international workshop on Database and Expert Systems Applications

作者： Bamha, M Univ Orleans CNRS LIFO F-45067 Orleans France

ISBN: (纸本)3540285660

The development of scalable parallel database systems requires the design of efficient algorithms for the join operation which is the most frequent and expensive operation in relational database systems. The join is also the most vulnerable operation to data skew and to the high cost of communication in distributed architectures. In this paper, we present a new parallel algorithm for join and multi-join operations on distributed architectures based on an efficient semi-join computation technique. This algorithm is proved to have optimal complexity and deterministic perfect load balancing. Its tradeoff between balancing overhead and speedup is analyzed using the BSP cost model which predicts a negligible join product skew and a linear speed-up. This algorithm improves our fa-join and sfa-join algorithms by reducing their communication and synchronization cost to a minimum while offering the same load balancing properties even for highly skewed data.

关键词： parallel processing systems

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Embedded reconfigurable DCT architectures using adder-based distributed arithmetic

Embedded reconfigurable DCT architectures using adder-based ...

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7th international workshop on Computer Architecture for Machine Perception, CAMP 2005

作者： Pai, Arjun K. Benkrid, Khaled Crookes, Danny

A hybrid adder-based distributed arithmetic (DA) architecture targeting a reconfigurable System-on-Chip (rSoC) platform has been presented. The work exemplifies hardware comparisons of three DA based discrete cosine transform (DCT) algorithms based on pure-RAM, mixed-RAM and CORDIC-based processors. Preliminary investigation involved evaluation of the DCT algorithms on a heterogeneous composition of domain-specific memory and logic building blocks. The architectures were simulated for functional validation on ModelSim SE v6.0 and compliance testing of these architectures was performed using a self-testing testbench. The motivation was to illustrate the modularity, regularity, symmetry, and recursive-decomposition properties of transform vector-matrix computations for a case study of discrete cosine transforms using adder-based DA. Further, the paper overviews existing DCT architectures and previews future reconfigurable computing devices and contributes towards a novel conjecture on future directions in the reconfigurable hardware landscape. The embedded reconfigurable computation array presented in this paper has an intermediate-grain framework unlike the fine-grained nature of the current FPGAs. © 2005 IEEE.

关键词： Computer architecture

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Load balancing parallel explicit state model checking

Load balancing parallel explicit state model checking

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proceedings of the 3rd international workshop on parallel Distributed Methods in Verification (PDMC 2004)

作者： Kumar, Rahul Mercer, Eric G. Verification and Validation Lab. Department of Computer Science Brigham Young University Provo United States

This paper first identifies some of the key concerns about the techniques and algorithms developed for parallel model checking;specifically, the inherent problem with load balancing and large queue sizes resultant in a static partition algorithm. This paper then presents a load balancing algorithm to improve the run time performance in distributed model checking, reduce maximum queue size, and reduce the number of states expanded before error discovery. The load balancing algorithm is based on generalized dimension exchange (GDE). This paper presents an empirical analysis of the GDE based load balancing algorithm on three different supercomputing architectures - distributed memory clusters, Networks of Workstations (NOW) and shared memory machines. The analysis shows increased speedup, lower maximum queue sizes and fewer total states explored before error discovery on each of the architectures. Finally, this paper presents a study of the communication overhead incurred by using the load balancing algorithm, which although significant, does not offset performance gains. © 2005 Elsevier B.V.

关键词： parallel processing systems

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Languages and Compilers for High Performance Computing: 17th international workshop, LCPC 2004. Revised Selected Papers

Languages and Compilers for High Performance Computing: 17th...

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17th international workshop on Languages and Compilers for High Performance Computing, LCPC 2004

The proceedings contain 33 papers from the Language and Compilers for High Performance Computing: 17th international workshop, LCPC 2004, Revised Selected Papers. The topics discussed include: an overview of the open research compiler;phase-based miss rate prediction across program inputs;speculative subword register allocation in embedded processors;implementation of parallel numerical algorithms using hierarchically tiled arrays;a geometric approach for partitioning n-dimensional non-rectangular iteration spaces;the use of traces for inlining in java programs;compiling high-level languages for vector architectures;and applying loop optimizations to object-oriented abstractions through general classification of array semantics.

关键词： Program compilers

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Program structuring algorithms for dynamically reconfigurable parallel systems based on redundant connection switches

Program structuring algorithms for dynamically reconfigurabl...

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3rd international Symposium on parallel and Distributed Computing (ISPDC 2004)/3rd international workshop on algorithms, Models and Tools for parallel Computing on Heterogeneous Networks (HeteroPar 04)

作者： Laskowski, E Polish Acad Sci Inst Comp Sci PL-01237 Warsaw Poland

ISBN: (纸本)0769522106

A new program graph structuring algorithm for dynamically reconfigurable multi-processor systems based on the look-ahead dynamic connection reconfiguration is presented. This architectural model enables elimination of connection reconfiguration time overheads. It consists in preparing link connections in advance in redundant connection switches in parallel with program execution. An application program is partitioned into sections, which are executed using such connections. parallel program scheduling in this environment incorporates graph partitioning problem. The new algorithm is based on list scheduling and a new iterative clustering heuristics for graph partitioning. The experimental results are presented, which compare performance of several graph partitioning heuristics for such environment.

关键词： parallel architectures interconnection networks scheduling

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parallelization of the GNU scientific library on heterogeneous systems

Parallelization of the GNU scientific library on heterogeneo...

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作者： Aliaga, J Almeida, F Badía, JM Barrachina, S Blanco, V Castillo, M Dorta, U Mayo, R Quintana, ES Quintana, G Rodríguez, C de Sande, F Univ Jaume I Depto Ingn & Ciencia Comp Castellon de La Plana 12071 Spain

ISBN: (纸本)0769522106

In this paper we present our joint efforts towards the development of a parallel version of the GNU Scientific Library for heterogeneous systems. Two well-known operations arising in discrete mathematics and sparse linear algebra allow us to describe the design and the implementation of the library, and to report experimental results on heterogeneous clusters of personal computers.

关键词： GNU Scientific Library scientific computing parallel algorithms and architectures heterogeneous parallel systems

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Analytic comparison of two advanced C language-based parallel programming models

Analytic comparison of two advanced C language-based paralle...

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作者： Marowka, A Hebrew Univ Jerusalem Sch Comp Sci & Engn Comp Aided Design Lab IL-91904 Jerusalem Israel

ISBN: (纸本)0769522106

There are two main approaches for designing parallel language. The first approach states that parallel computing demands new programming concepts and radical intellectual changes regarding the way we think about programming, as compared to sequential computing. Therefore, the design of such a parallel language must present new constructs and new programming methodologies. The second approach states that there is no need to reinvent the wheel, and serial languages can be extended to support parallelism. The motivation behind this approach is to keep the language as friendly as possible for the programmer who is the main bridge toward wider acceptance of the new language. In this paper we present a qualitative evaluation of two contemporary parallel languages: OpenMP-C and Unified parallel C (UPC). Both are explicit parallel programming languages based on the ANSI C standard. OpenMP-C was designed for shared-memory architectures and extends the base-language by using compiler directives that annotate the original source-code. On the other hand, UPC was designed for distribute-shared memory architectures and extends the base-language by new parallel constructs. We deconstruct each parallel language into its basic components, show examples, make a detailed analysis, compare them, and finally draw some conclusions.

关键词： parallel processing systems

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JIST: Just-in-time scheduling translation for parallel processors

JIST: Just-in-time scheduling translation for parallel proce...

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proceedings - ISPDC 2004: Third international Symposium on parallel and Distributed Computing/HeteroPar '04: Third international workshop on algorithms, Models and Tools for parallel Computing on Heterogeneous Networks

作者： Agosta, Giovanni Reghizzi, Stefano Crespi Falauto, Gerlando Sykora, Martino Politecnico di Milano Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32 20133 Milano Italy

ISBN: (纸本)0769522106

The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JJST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JIT compiler. Further optimizations are discussed. © 2004 IEEE.

关键词： Scheduling

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