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检索条件"任意字段=Proceedings of the International Workshop on Algorithms and Parallel VSLI Architectures"

共 181 条记录，以下是71-80 订阅

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16th international workshop on Languages and Compilers for parallel Computing, LCPC 2003

16th International Workshop on Languages and Compilers for P...

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16th international workshop on Languages and Compilers for parallel Computing, LCPC 2003

ISBN: (纸本)9783540246442

The proceedings contain 35 papers. The special focus in this conference is on Languages and Compilers for parallel Computing. The topics include: Search space properties for mapping coarse-grain pipelined FPGA applications;adapting convergent scheduling using machine-learning;time-sensitive, flow-specific profiling at runtime;a hierarchical model of reference affinity;cache optimization for coarse grain task parallel processing using inter-array padding;compiler-assisted cache replacement;memory-constrained data locality optimization for tensor contractions;compositional development of parallel programs;supporting high-level abstractions through XML technology;applications of HP java;programming for locality and parallelism with hierarchically tiled arrays;evaluating the impact of programming language features on the performance of parallel applications on cluster architectures;putting polyhedral loop transformations to work;index-association based dependence analysis and its application in automatic parallelization;improving the performance of morton layout by array alignment and loop unrolling;space-aware programming for networks of embedded systems;memory redundancy elimination to improve application energy efficiency;adaptive MPI polynomial-time algorithms for enforcing sequential consistency in SPMD programs with arrays;a system for automating application-level checkpointing of MPI programs;the power of belady’s algorithm in register allocation for long basic blocks;load elimination in the presence of side effects, concurrency and precise exceptions;a preliminary study on the vectorization of multimedia applications for multimedia extensions;a data cache with dynamic mapping;compiler-based code partitioning for intelligent embedded disk processing;compilation for nanocontrollers and slice-hoisting for array-size inference in MATLAB.

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Scheduling with QoS in parallel I/O systems 04

Scheduling with QoS in parallel I/O systems

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proceedings of the international workshop on Storage network architecture and parallel I/Os

作者： Ajay Gulati Peter Varman Rice University

ISBN: (纸本)9781450378222

parallel I/O architectures are increasingly deployed for high performance computing and in shared data centers. In these environments it is desirable to provide QoS-based allocation of disk bandwidth to different applications sharing the I/O system. In this paper, we introduce a model of disk bandwidth allocation, and provide efficient scheduling algorithms to assign the bandwidth among the concurrent applications.

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An applications-based approach to measuring DSP efficiency 1

An applications-based approach to measuring DSP efficiency

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1st IEEE international workshop on Electronic Design, Test and Applications

作者： Chase, JG Pretty, C Bedarida, A Bettler, P Univ Canterbury Canterbury New Zealand

ISBN: (纸本)0769514537

The current trend in DSP architecture is to widen the data path and augment computational power, often at the expense of issues that significantly impact the ability to utilize its computation. With today's highly parallel architectures and complex application spaces DSP selection has become overly complicated and the addition of special instructions that support intensive algorithms, while maximizing parallelism, has further complicated the issue. Typically, a system designer may rely on simple cycle counts, discounting the impact of architecture, efficiency and power consumption. The simple cycle efficiency metric presented clearly illustrates that the ability to utilize the theoretically available computation is a significant measure of DSP performance for a given application. This metric is presented as an application-oriented design tool and is employed to compare the dual-execution unit, dynamically reconfigurable Carmel DSP with similar architectures.

关键词： parallel architectures

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An applications-based approach to measuring DSP efficiency

An applications-based approach to measuring DSP efficiency

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IEEE international workshop on Electronic Design, Test and Applications (DELTA)

作者： J.G. Chase C. Pretty A. Bedarida P. Bettler University of Canterbury UK Infineon Technologies Corporation USA

ISBN: (纸本)0769514537

关键词： Digital signal processing Computer architecture Energy consumption Space technology Silicon Memory architecture parallel architectures parallel processing Spirals Mobile computing

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Control architecture of parallel and spherical driving simulators and related human factors

Control architecture of parallel and spherical driving simul...

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10th IEEE international workshop on Robot and Human Interactive Communication

作者： Maza, M Val, S Baselga, S Univ Zaragoza Dept Mech Engn Zaragoza 50015 Spain

ISBN: (纸本)0780372220

Driving simulators are a powerful tool that enables to carry on studies on different fields, like human behavior and response to stimuli, control algorithms to simulate vehicle motion with high fidelity, etc. Research on safety factors in land vehicles requires the use of advanced techniques. Thus, the implementation of a simulator motion base drive logic able to imitate typical vehicle maneuvers requires a good control architecture, giving the user a complete sensation of reality. In a general way, any land vehicle motion can be simulated by changing and adapting parameters either in the simulator motion base control algorithm or in the vehicle computer model. Thus, the Mechanical Engineering Department of Zaragoza University Transportation Area (Spain) has developed two types of simulator architectures, based on the classical 6-DOF Stewart platform and on the original 4-DOF spherical platform. The experience gained in the last years with the development and use of such simulators leads to some interesting conclusions related to the general simulator architecture, control algorithms and related human factors.

关键词： Automobile driver simulators

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20th international Conference on Computer Safety, Reliability and Security, SAFECOMP 2001

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20th international Conference on Computer Safety, Reliability and Security, SAFECOMP 2001

ISBN: (纸本)3540426078

The proceedings contain 23 papers. The special focus in this conference is on Computer Safety, Reliability and Security. The topics include: Designing safety into medical decisions and clinical processes;security assessments of safety critical systems using HAZOPs;network security for substation automation systems;a bayesian belief network for reliability assessment;checking general safety criteria on UML statecharts;safety functions versus control functions;a fail-safe dual channel robot control for surgery applications;modelling the human in human factors;analyzing human-machine interactions in safety-critical systems;analysis of incidents involving interactive systems;experimental evaluation of fault handling mechanisms;the cots debate in perspective;an investigation on mutation strategies for fault injection into RDD-100 models;a comparison study of the behavior of equivalent algorithms in fault injection experiments in parallel superscalar architectures;the effectiveness of statistical testing when applied to logic systems;the key to formal specification of safety requirements;formal support for fault modeling and analysis;project experience with IEC 61508 and its consequences;about the design of distributed control systems and tuning of database audits to improve scheduled maintenance in communication systems.

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Control architecture of parallel and spherical driving simulators and related human factors

Control architecture of parallel and spherical driving simul...

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IEEE international workshop on Robot and Human Communication (ROMAN)

作者： M. Maza S. Val S. Baselga Transportation Area Mechanical Engineering Department University of Zaragoza Zaragoza Spain

Driving simulators are a powerful tool that enable one to carry out studies in different fields, like human behavior and response to stimuli, control algorithms to simulate vehicle motion with high fidelity, etc. Research on safety factors in land vehicles requires the use of advanced techniques. Thus, the implementation of a simulator motion base drive logic, able to imitate typical vehicle maneuvers, requires a good control architecture, giving the user a complete sensation of reality. In a general way, any land vehicle motion can be simulated by changing and adapting parameters either in the simulator motion base control algorithm or in the vehicle computer model. Thus, the authors developed two types of simulator architectures, based on the classical 6-DOF Stewart platform and on the original 4-DOF spherical platform. The experience gained in the last years with the development and use of such simulators leads to some interesting conclusions related to the general simulator architecture, control algorithms and related human factors.

关键词： Human factors Computational modeling Vehicle driving Motion control Biological system modeling Automotive engineering Land vehicles Computer architecture Computer simulation Transportation

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Runtime predictability of loops

Runtime predictability of loops

引用

IEEE international workshop/Symposium on Workload Characterization

作者： M.R. de Alba D.R. Kaeli Department of Electrical and Computer Engineering Northeastern University Boston MA USA

ISBN: (纸本)0780373154

To obtain the benefits of aggressive, wide-issue, architectures, a large window of valid instructions must be available. While researchers have been successful in obtaining high accuracies with a range of dynamic branch predictors, there still remains the need for more aggressive instruction delivery. Loop bodies possess a large amount of spatial and temporal locality. A large percentage of a program's entire execution can be attributed to code found in loop bodies. If we retain this code in a buffer or the cache, we do not have to refetch this code on subsequent loop iterations., Loops tend to iterate multiple times before exiting, thus providing us with the opportunity to speculatively issue multiple iterations. While some loops can be unrolled by a compiler many contain conditional branches. The number of times a loop iterates may be dependent on a program variable. These issues can hinder our ability to speculatively issue multiple iterations of a loop. If we are able to profile loops during runtime, we can use this information to more accurately issue speculative paths through loop bodies. In this paper we present a characterization of loop execution across the SPECint2000 benchmark suite. We intend for this study to serve as a guide in the selection of design parameters of a loop path predictor We characterize the patterns exhibited during multiple visits to a loop body. We present the design of a table that records path-based loop execution history and allows us to predict multiple loop iterations dynamically.

关键词： Runtime Dynamic range History Computer aided instruction Computer architecture Programming profession Iterative algorithms parallel processing Terminology

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A parallel spatial join framework using PMR-Quadtrees 11

A parallel spatial join framework using PMR-Quadtrees

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11th international workshop on Database and Expert Systems Applications

作者： Lima, AAB Esperança, C Mattoso, M Univ Fed Rio de Janeiro Dept Comp Sci COPPE BR-21945970 Rio De Janeiro Brazil

ISBN: (纸本)0769506801

Spatial join is the most important and complex operation in spatial databases. Therefore, there is a lot of ongoing research presenting algorithms and data structures to efficiently process spatial joins. ill this work we present a parallel solution for spatial join processing with a dynamic load balance strategy. We have implemented PMR-Quadtrees [14] on top of persistent object structures using an Object Oriented Database Server.

关键词： Computer science Data structures Database systems Load management Memory architecture Object oriented databases parallel architectures parallel processing Scalability Spatial databases

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Choice of SM/DM parallel ANN implementation for embedded applications

Choice of SM/DM parallel ANN implementation for embedded app...

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7th IEEE international Conference and workshop on the Engineering of Computer Based Systems (ECBS 2000)

作者： Dvorak, Vaclav Cejka, Rudolf Brno Univ of Technology Brno Czech Republic

This paper examines implementations of a multi-layer perceptron (MLP) on bus-based shared memory (SM) and on distributed memory (DM) multiprocessor systems. The goal has been to optimize HW and SW architectures in order to obtain the fastest response possible. Prototyping parallel MLP algorithms for up to 8 processing nodes with the DM as well as SM memory was done using CSP-based TRANSIM tool. The results of prototyping MLPs of different sizes on various number of processing nodes demonstrate the feasible speedups, efficiency and time responses for the given CPU speed, link speed or bus bandwidth.

关键词： Multilayer neural networks

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