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Performance analysis of an adaptive dynamic grid-based approach to data distribution management 06

Performance analysis of an adaptive dynamic grid-based appro...

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10th ieee International symposium on distributed Simulation and Real-Time Applications

作者： Boukerche, Azzedine Gu, YunFeng Araujo, Regina B. Univ Ottawa PARADISE Res Lab Ottawa ON K1N 6N5 Canada Univ Fed Sao Carlos BR-13560 Sao Carlos SP Brazil

ISBN: (纸本)0769526977

Data Distribution Management (DDM) plays a key role in traffic volume control of large-scale distributed simulations. In recent years, several solutions have been devised to make DDM more efficient and adaptive to different traffic conditions. Examples of such systems include Region-Based, Fixed Grid-Based, Hybrid, and Dynamic Grid-Based (DGB) schemes. However, less effort has been made to improve the processing performance of DDM techniques. This paper presents a novel DDM scheme called the Adaptive Dynamic Grid-Based (ADGB) scheme that optimizes DDM time through analysis of Matching performance. ADGB uses an advertising scheme in which information about the target cell involved in the process of matching subscribers to publishers is known in advance. An important concept known as Distribution Rate (DR) is devised. DR represents the relative processing load and traffic volume generated at each federate. The Matching performance and DR are used as part of the ADGB method to select, throughout the simulation, the devised. advertisement scheme that achieves maximum gain with acceptable network traffic overhead. Performance estimation and analysis of ADGB have shown that given an ideal Matching probability, an efficiency gain of a maximum of 66% over the DGB scheme can be achieved. The novelty of the ADGB scheme is its focus on improving peirformance, an important (and often forgotten) goal of DDM strategies.

关键词： Performance analysis distributed decision making Traffic control Performance gain Programmable control Adaptive control Large-scale systems Advertising Telecommunication traffic Communication system traffic control

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An efficient and scalable parallel algorithm for out-of-core isosurface extraction and rendering 20

An efficient and scalable parallel algorithm for out-of-core...

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20th ieee International parallel and distributed processing symposium, IPDPS 2006

作者： Qin, Wang JaJa, Joseph Varshney, Amitabh University of Maryland Institute for Advanced Computer Studies Dept. of Electrical and Computer Engineering College Park MD 20742 United States University of Maryland Institute for Advanced Computer Studies Dept. of Computer Science College Park MD 20742 United States

ISBN: (纸本)1424400546

We consider the problem of isosurface extraction and rendering for large scale time varying data. Such datasets have been appearing at an increasing rate especially from physics-based simulations, and can range in size from hundreds of gigabytes to tens of terabytes. We develop a new simple indexing scheme, which makes use of the concepts of the interval tree and the span space data structures. The new scheme enables isosurface extraction and rendering in I/O optimal time, using more compact indexing structure and more effective bulk data movement than the previous schemes. Moreover, our indexing scheme can be easily extended to a multiprocessor environment in which each processor has access to its own local disk. The resulting parallel algorithm is provably efficient and scalable. That is, it achieves load balancing across the processors independent of the isovalue, with almost no overhead in the total amount of work relative to the sequential algorithm. We conduct a large number of experimental tests on the University of Maryland Visualization Cluster using the Richtmyer-Meshkov instability dataset, and obtain results that consistently validate the efficiency and the scalability of our algorithm. © 2006 ieee.

关键词： parallel algorithms

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Fault and intrusion tolerance of wireless sensor networks 20

Fault and intrusion tolerance of wireless sensor networks

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20th ieee International parallel and distributed processing symposium, IPDPS 2006

作者： Wang, Liang-Min Ma, Jian-Feng Wang, Chao Kot, Alex Chichung IEEE Xidian University Key Laboratory of CNIS Education Ministry Xi'an Shaanxi 710071 China Nanyang Technological University School of Electrical and Electronic Engineering 639798 Singapore Singapore

ISBN: (纸本)1424400546

The following three questions should be answered in developing new topology with more powerful ability to tolerate node-failure in wireless sensor network. First, what is node-failure tolerance of topologies? Second, how to evaluate this tolerance ability? third, which type of topologies is more efficient in tolerating node-failure? Without giving the answers, the existing work regards fault-tolerance topology as the multiply connected graph, and use the connectivity of the graph as the standard to evaluate tolerance ability. In this paper, we argue that fault tolerance of topologies is not equivalent to the connectivity of multiply connected graph by illustrating two concrete examples. Then the definition of node-failure tolerance is presented. According fault and intrusion, the two sources of failure nodes, we define fault tolerance and intrusion tolerance as the standards to evaluate the tolerance ability of topologies, and analyze the tolerance performance of hierarchical structure of wireless sensor network by using these standards. Finally, the function relation between hierarchical topology and its tolerance abilities of fault and intrusion is obtained, and an obvious corollary is that fault tolerance increase with the ratio of cluster head hierarchical structure, but with the intrusion tolerance decreasing. © 2006 ieee.

关键词： Wireless telecommunication systems

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Optimizing distributed Data Mining applications based on object clustering methods

Optimizing Distributed Data Mining applications based on obj...

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International symposium on parallel Computing in Electrical Engineering

作者： Fiolet, V. Laskowski, E. Olejnik, R. Masko, L. Toursel, B. Tudruj, M. Univ Sci & Technol Lille UMR CNRS 8022 Lab Informat Fondamentale Lille Lille France Univ Mons Inst Comp Sci Mons Belgium Polish Acad Sci Inst Comp Sci PL-00901 Warsaw Poland

ISBN: (纸本)0769525547

The exponential computational cost involved in traditional data mining methods enforces search for less complex new algorithms. Especially, data mining on Grid is a challenge due to the lack of shared memory in Grid computing, which puts special attention to communication optimization. The aim of the DisDaMin project (distributed Data Mining), descibed in the paper, is solving data mining problems by using new distributed algorithms intented for execution in Grid environments. The DisDaMin implements intelligent fragmentation of data by clustering methods and asynchronous collaborative processing adjusted to Grid environments. The DG-ADAJ environment Provides adaptive control of distributed applications written in Java for Desktop Grid. It constitutes a component-based middleware, which allows for optimized distribution of applications on clusters of Java Virtual Machines, monitoring of application execution and dynamic on-line balancing of processing and communication. The DG-ADAJ system provides a middleware Platform for Desktop Grid that could be used as a deployment base for DisDaMin algorithms. In this paper we propose static object placement optimization algorithms for fragmentation of data in the DisDaMin project. The algorithms use DG-ADAJ's object clustering methods to provide optimized localprocessing on each node with minimized inter-node communication.

关键词： Grid data mining clustering Java middleware

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Memory-efficient Kronecker algorithms with applications to the modelling of parallel systems

Memory-efficient Kronecker algorithms with applications to t...

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International Workshop on Performance Modeling, Evaluation, and Optimization of parallel and distributed Systems

作者： Benoit, Anne Plateau, Brigitte Stewart, William J. ENSIMAG Lab ID IMAG Antenne Montbonnot F-38330 Montbonnot St Martin France N Carolina State Univ Dept Comp Sci Raleigh NC 27695 USA

ISBN: (纸本)0769519261

We present a new algorithm for computing the solution of large Markov chain models whose generators can be represented in the form of a generalized tensor algebra, such as networks of stochastic automata. The tensor structure inherently involves a product state space but, inside this product state space, the actual reachable state space can be much smaller. For such cases, we propose an improvement of the standard numerical algorithm, the so-called "shuffle algorithm", which necessitates only vectors of the size of the actual state space. With this contribution, numerical algorithms based on tensor products can now handle larger models. (C) 2006 Elsevier B.V. All rights reserved.

关键词： large and sparse Markov chains stochastic automata networks generalized tensor algebra vector-descriptor multiplication shuffle algorithm

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A method to improve structural modeling based on conserved domain clusters 20

A method to improve structural modeling based on conserved d...

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20th ieee International parallel and distributed processing symposium, IPDPS 2006

作者： Zhang, Fa Xu, Lin Yuan, Bo IEEE China Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Department of Biomedical Information Ohio State University Columbus OH 43210 United States Institute of Computing Technology Graduate Schools Chinese Academy of Sciences Beijing 100080 China Department of Biomedical Information and Pharmacology Ohio State University Columbus OH 43210 United States

ISBN: (纸本)1424400546

Homology modeling requires an accurate alignment between a query sequence and its homologs with known three-dimensional (3D) information. Current structural modeling techniques largely use entire protein chains as templates, which are selected based only on their sequence alignments with the queries. Protein can be largely described as combinations of conserved domains, and already more than two-third of the known protein domains can be found in the Protein Data Bank (PDB). We presented a method to improve structural modeling based on conserved domain clusters. First, we searched and mapped all the InterPro domains in the entire PDB, partitioned and clustered homologous domains into the domain-based template library. For each of the resulting clusters created, a multiple structural alignment was generated based only on the 3D coordinates of all the residues involved. Then we used the structural alignments as anchors to increase the alignment accuracy between a query and its templates, and consequently improve the quality of predicted structure for query protein. We implemented the method on DAWNING 4000A cluster system. The preliminary results show that our domain-based template library and the structure-anchored alignment protocol can be used for the partial prediction for a majority of known protein sequences with better qualities. © 2006 ieee.

关键词： Natural sciences computing

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New parallel simulation techniques of DEVS and cell-DEVS in CD++

New parallel simulation techniques of DEVS and cell-DEVS in ...

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39th Annual Simulation symposium, 2006

作者： Glinsky, Ezequiel Wainer, Gabriel Dept. of Systems and Computer Engineering Carleton University 4456 Mackenzie Building 1125 Colonel By Drive Ottawa Ont. K1S 5B6 Canada

ISBN: (纸本)0769525598

DEVS is a sound formal modeling and simulation (M&S) framework based on generic dynamic system concepts. Cell-DEVS is a formalism for cell-shaped models based on DEVS. This work presents a new simulation technique for execution of DEVS and Cell-DEVS models in parallel/distributed environments. The parallel simulator is based on Time Warp, and developed as a new simulation engine for CD++, a M&S toolkit that implements DEVS and Cell-DEVS theories. The technique uses a non-hierarchical approach that simplifies the structure of the simulator and reduces the communication overhead. The results obtained allowed us to achieve considerable speedups. © 2006 ieee.

关键词： parallel processing systems

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A parallel hardware architecture for fast Gaussian elimination over GF(2)

A parallel hardware architecture for fast Gaussian eliminati...

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14th Annual ieee symposium on Field-Programmable Custom Computing Machines

作者： Bogdanov, A. Mertens, M. C. Paar, C. Pelzl, J. Rupp, A. Ruhr Univ Bochum Horst Gortz Inst IT Secur Univ Str 150 D-4630 Bochum Germany

ISBN: (纸本)0769526616

This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture can solve any regular and (uniquely solvable) overdetermined linear system of equations (LSE) and is not limited to matrices of a certain structure. Besides solving LSEs, the architecture at hand can also accomplish the related problem of matrix inversion extremely fast. Its average running time for n x n binary matrices with uniformly distributed entries equals 2n (clock cycles) as opposed to about 1/4n(3) in software. The average running time remains very close to 2n for matrices with densities much greater or lower than 0.5. The architecture has a worst-case time complexity of O(n(2)) and also a space complexity of O(n(2)). With these characteristics the architecture is particularly suited to efficiently solve medium-sized LSEs as they for example appear in the cryptanalysis of certain stream cipher classes. Moreover, we propose a hardware-optimized algorithm for matrix-by-matrix multiplication over GF(2) which runs in linear time and quadratic space on a similar architecture. This opens up the possibility of building a more complex architecture for efficiently solving larger LSEs by means of Strassen's algorithm which could significantly improve the time complexity of algebraic attacks on various ciphers. As proof-of-concept we realized our architecture on a contemporary low-cost FPGA. The implementation for a 50 x 50 LSE can be clocked with a frequency of up to 300 MHz and computes the solution in 0.33 mu s on average.

关键词： parallel processing systems

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proceedings. 19th ieee International parallel and distributed processing symposium

Proceedings. 19th IEEE International Parallel and Distribute...

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International symposium on parallel and distributed processing (IPDPS)

作者： R.F. van der Wijngaart M. Frumkin V.C. Bhavsar E. Aubanel T. Kielmann Vrije Univ. Amsterdam

HIPS-HPGC 2005 is a full-day workshop, focusing on high-performance grid computing and high-level parallel programming models. The papers deal with component models and service-based systems for grids, emphasizing on experiences with existing systems. Also the papers report on the state of the art of grid applications, both for academic and industrial problems

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A practical fast parallel routing architecture for Clos networks 06

A practical fast parallel routing architecture for Clos netw...

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2nd ACM/ieee symposium on Architectures for Networking and Communications Systems, ANCS 2006

作者： Zheng, S.Q. Gumaste, Ashwin Lu, Enyue Dept. of Computer Science University of Texas at Dallas Richardson TX 75083 United States School of Information Tech. Indian Institute of Technology Bombay India Dept. Math and CS Salisbury University Salisbury MD 21801 United States

ISBN: (纸本)1595935800

Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos networks, sequential routing algorithms are too slow, and all known parallel algorithms are not practical. We present the algorithm-hardware codesign of a unified fast parallel routing architecture called distributed pipeline routing (DPR) architecture for rearrangeable nonblocking and strictly nonblocking Clos networks. The DPR architecture uses a linear interconnection structure and processing elements that performs only shift and logic AND operations. We show that a DPR architecture can route any permutation in rearrangeable nonblocking and strictly nonblocking Clos networks in O(N) time. The same architecture can be used to carry out control of any group of connection/disconnection requests for strictly nonblocking Clos networks in O(N) time. Several speeding-up techniques are also presented. This architecture is applicable to packet and circuit switches of practical sizes. Copyright 2006 ACM.

关键词： Routing protocols

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