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Facing the challenges of multicore processor technologies using autonomic system software 06

Facing the challenges of multicore processor technologies us...

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International symposium on parallel and distributed processing (IPDPS)

作者： D. Nikolopoulos Department of Computer Science College of William and Mary Williamsburg VA USA

ISBN: (纸本)9781424400546

Summary form only given. Multicore processor technologies, which appear to dominate the processor design landscape, require a shift of paradigm in the development of programming models and supporting environments for scientific and engineering applications. System software for multicore processors needs to exploit fine-grain concurrent execution capabilities and cope with deep, non- uniform memory hierarchies. Software adaptation to multicore technologies needs to happen even as hardware platforms change underneath the software. Last but not least, due to the extremely high compute density of chip multiprocessing components, system software needs to increase its energy-awareness and treat energy and temperature distribution as first-class optimization targets. Unfortunately, energy awareness is most often at odds with high performance. In the first part of this talk, the author discusses some of the major challenges of software adaptation to multicore technologies and motivate the use of autonomic, self-optimizing system software, as a vehicle for both high performance portability and energy-efficient program execution. In the second part of the talk, the author presents ongoing research in runtime environments for dense parallel systems built from multicore and SMT components, and focus on two topics, polymorphic multithreading, and power-aware concurrency control with quality-of-service guarantees. In the same context, the author discusses enabling technologies for improved software autonomy via dynamic runtime optimization, including continuous hardware profilers, and online power-efficiency predictors

关键词： Multicore processing System software Hardware Process design Design engineering Application software distributed computing Temperature distribution Software performance Vehicles

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parallel genetic algorithm for SPICE model parameter extraction 06

Parallel genetic algorithm for SPICE model parameter extract...

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International symposium on parallel and distributed processing (IPDPS)

作者： Yiming Li Yen-Yu Cho Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781424400546

Models of simulation program with integrated circuit emphasis (SPICE) are currently playing a central role in the connection between circuit design and chip fabrication communities. An automatic model parameter extraction system that simultaneously integrates evolutionary and numerical optimization techniques for optimal characterization of very large scale integration (VLSI) devices has recently been advanced (Li and Cho, 2004). In this paper, to accelerate the extraction process, a parallelization of the genetic algorithm (GA) for VLSI device equivalent circuit model parameter extraction is developed. The GA implemented in the extraction system is mainly parallelized with a diffusion scheme on a PC-based Linux cluster with message passing interface libraries. parallelization of GA is governed by many factors, which affect the quality of extracted parameters and its efficiency. The diffusion GA is superior to an isolated GA, and the superiority of the diffusion GA is significant when the number of devices to be optimized is increased. Theoretical estimation and preliminary implementation show that there is an optimal number of processors with respect to the number of devices to be extracted. Benchmark results, such as speedup and efficiency including accuracy of extraction are presented and discussed for different sets of realistic multiple VLSI devices to show the robustness and efficiency of the method. We believe that the practical implementation of the parallel GA approach benefits the engineering of SPICE model parameter extraction in modern electronic industry.

关键词： Genetic algorithms SPICE Parameter extraction Very large scale integration Integrated circuit modeling Circuit synthesis Chip scale packaging Acceleration Equivalent circuits Linux

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Adaptive connection management for scalable MPI over InfiniBand 06

Adaptive connection management for scalable MPI over InfiniB...

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International symposium on parallel and distributed processing (IPDPS)

作者： Weikuan Yu Qi Gao D.K. Panda Network-Based Computing Laboratory Department of Computer Science & Engineering Ohio State Uinversity USA

ISBN: (纸本)9781424400546

Supporting scalable and efficient parallel programs is a major challenge in parallel computing with the widespread adoption of large-scale computer clusters and supercomputers. One of the pronounced scalability challenges is the management of connections between parallel processes, especially over connection-oriented interconnects such as VIA and InfiniBand. In this paper, we take on the challenge of designing efficient connection management for parallel programs over InfiniBand clusters. We propose adaptive connection management (ACM) to dynamically control the establishment of InfiniBand reliable connections (RC) based on the communication frequency between MPI processes. We have investigated two different ACM algorithms: an on-demand algorithm that starts with no InfiniBand RC connections; and a partial static algorithm with only 2 * logN number of InfiniBand RC connections initially. We have designed and implemented both ACM algorithms in MVAPICH to study their benefits. Two mechanisms have been exploited for the establishment of new RC connections: one using InfiniBand unreliable datagram and the other using InfiniBand connection management. For both mechanisms, MPI communication issues, such as progress rules, reliability and race conditions are handled to ensure efficient and lightweight connection management. Our experimental results indicate that ACM algorithms can benefit parallel programs in terms of the process initiation time, the number of active connections, and the resource usage. For parallel programs on a 16-node cluster, they can reduce the process initiation time by 15% and the initial memory usage by 18%.

关键词： Clustering algorithms parallel processing Large-scale systems Concurrent computing Supercomputers Scalability Programmable control Adaptive control Radio control Communication system control

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Exploiting programmable network interfaces for parallel query execution in workstation clusters 06

Exploiting programmable network interfaces for parallel quer...

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International symposium on parallel and distributed processing (IPDPS)

作者： V.S. Kumar M.J. Thazhuthaveetil R. Govindarajan Supercomputer Edn. and Research Centre Indian Institute of Science Bangalore India Department of Computer Science and Automation Supercomputer Edn. and Research Centre Indian Institute of Science Bangalore India

ISBN: (纸本)9781424400546

Workstation clusters equipped with high performance interconnect having programmable network processors facilitate interesting opportunities to enhance the performance of parallel application run on them. In this paper, we propose schemes where certain application level processing in parallel database query execution is performed on the network processor. We evaluate the performance of TPC-H queries executing on a high end cluster where all tuple processing is done on the host processor, using a timed Petri net model, and find that tuple processing costs on the host processor dominate the execution time. These results are validated using a small cluster. We therefore propose 4 schemes where certain tuple processing activity is offloaded to the network processor. The first 2 schemes offload the tuple splitting activity - computation to identify the node on which to process the tuples, resulting in an execution time speedup of 1.09 relative to the base scheme, but with I/O bus becoming the bottleneck resource. In the 3rd scheme in addition to offloading tuple processing activity, the disk and network interface are combined to avoid the I/O bus bottleneck, which results in speedups up to 1.16, but with high host processor utilization. Our 4th scheme where the network processor also performs apart of join operation along with the host processor, gives a speedup of 1.47 along with balanced system resource utilizations. Further we observe that the proposed schemes perform equally well even in a scaled architecture i.e., when the number of processors is increased from 2 to 64

关键词： Network interfaces Intelligent networks Workstations Application software Databases Concurrent computing Costs High performance computing Supercomputers Bandwidth

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Ad-hoc distributed spatial joins on mobile devices 06

Ad-hoc distributed spatial joins on mobile devices

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International symposium on parallel and distributed processing (IPDPS)

作者： P. Kalnis N. Mamoulis S. Bakiras Xiaochen Li Department of Computer Science National University of Singapore Singapore Department of Computer Science University of Hong Kong Hong Kong China Department of Computer Science Hong Kong University of Science and Technology Hong Kong China

ISBN: (纸本)9781424400546

PDAs, cellular phones and other mobile devices are now capable of supporting complex data manipulation operations. Here, we focus on ad-hoc spatial joins of datasets residing in multiple non-cooperative servers. Assuming that there is no mediator available, the spatial joins must be evaluated on the mobile device. Contrary to common applications that consider the cost at the server side, our main issue is the minimization of the transferred data, while meeting the resource constraints of the device. We show that existing methods, based on partitioning and pruning, are inadequate in many realistic situations. Then, we present novel algorithms that estimate the data distribution before deciding the physical operator independently for each partition. Our experiments with a prototype implementation on a WiFi-enabled PDA, suggest that the proposed methods outperform the competitors in terms of efficiency and applicability

关键词： Personal digital assistants Costs Computer science Spatial databases Cellular phones Mobile computing Partitioning algorithms Prototypes Mobile handsets Navigation

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Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search

Placement and routing of Boolean functions in constrained FP...

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International symposium on parallel and distributed processing (IPDPS)

作者： M.R. del Solar J.M.S. Perez J.A.G. Pulido M.A.V. Rodriguez Department de Informática Escuela Politécnica Caceres Spain

In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks, on EDIF format, of Boolean functions to be implemented. They are processed by a parser in order to obtain an internal representation which is able to be processed by a genetic algorithm (GA) tool. This tool develops the placement and routing tasks, considering possible restricted area into the FPGA. In order to help to the GA to make the routing stage we have added a local search procedure. That local search gets a path between two points without considering neither their placement nor the restricted areas among them. The GA is fully customizable, featuring the ability to work with one or several islands. The experiments have verified that using distributing execution improves the costs and speeds up the convergence towards better results in smaller slots of time

关键词： Routing Boolean functions Field programmable gate arrays Genetic algorithms Wire Circuits Biological cells Genetic programming Design automation Libraries

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D1HT: a distributed one hop hash table 06

D1HT: a distributed one hop hash table

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International symposium on parallel and distributed processing (IPDPS)

作者： L.R. Monnerat C.L. Amorim Comput. & Syst. Eng. Fed. Univ. of Rio de Janeiro Brazil COPPE-Computer and Systems Engineering Federal University of Rio de Janeiro Brazil

ISBN: (纸本)9781424400546

distributed hash tables (DHTs) have been used in a variety of applications, but most DHTs so far have opted to solve lookups with multiple hops, which sacrifices performance in order to keep little routing information and minimize maintenance traffic. In this paper, we introduce D1HT, a novel single hop DHT that is able to maximize performance with reasonable maintenance traffic overhead even for huge and dynamic peer-to-peer (P2P) systems. We formally define the algorithm we propose to detect and notify any membership change in the system, prove its correctness and performance properties, and present a quarantine-like mechanism to reduce the overhead caused by volatile peers. Our analyses show that D1HT has reasonable maintenance bandwidth requirements even for very large systems, while presenting at least twice less bandwidth overhead than previous single hop DHT

关键词： Routing Bandwidth Peer to peer computing Telecommunication traffic Application software Delay distributed computing Systems engineering and theory Change detection algorithms Mechanical factors

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Topology-aware task mapping for reducing communication contention on large parallel machines

Topology-aware task mapping for reducing communication conte...

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International symposium on parallel and distributed processing (IPDPS)

作者： T. Agarwal A. Sharma A. Laxmikant L.V. Kale University of Illinois at Urbana-Champaign University of Illinois at Urbana-Champaign Urbana IL US Univ. of Illinois at Urbana-Champaign IL USA

Communication latencies constitute a significant factor in the performance of parallel applications. With techniques such as wormhole routing, the variation in no-load latencies became insignificant, i.e., the no-load latencies for far-away processors were not significantly higher (and too small to matter) than those for nearby processors. Contention in the network is then left as the major factor affecting latencies. With networks such as fat-trees of hypercubes, with number of wires growing as P log P, even this is not a very significant factor. However, for torus and grid networks now being used in large machines such as BlueGene/L and the Cray XT3, such contention becomes an issue. We quantify the effect of this contention with benchmarks that vary the number of hops traveled by each communicated byte. We then demonstrate a process mapping strategy that minimizes the impact of topology by heuristically minimizing the total number of hop-bytes communicated. This strategy, and its variants, are implemented in an adaptive runtime system in Charm++ and adaptive MPI, so it is available for a broad class of applications.

关键词： parallel machines Delay Concurrent computing Computer networks Multiprocessor interconnection networks Network topology Jacobian matrices Routing Hypercubes Wires

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A simulator for parallel applications with dynamically varying compute node allocation

A simulator for parallel applications with dynamically varyi...

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International symposium on parallel and distributed processing (IPDPS)

作者： B. Schaeli B. Gerlach R.D. Hersch School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Switzerland

Dynamically allocating computing nodes to parallel applications is a promising technique for improving the utilization of cluster resources. We introduce the concept of dynamic efficiency which expresses the resource utilization efficiency as a function of time. We propose a simulation framework which enables predicting the dynamic efficiency of a parallel application. It relies on the DPS parallelization framework to which we add direct execution simulation capabilities. The high level flow graph description of DPS applications enables the accurate simulation of parallel applications without needing to modify the application code. Thanks to partial direct execution, simulation times and memory requirements may be reduced. In simulations under partial direct execution, the application's parallel behavior is simulated thanks to direct execution, and the duration of individual operations is obtained from a performance prediction model or from prior measurements. We verify the accuracy of our simulator by comparing the effective running time, respectively the dynamic efficiency, of parallel program executions with the running time, respectively the dynamic efficiency, predicted by the simulator. These comparisons are performed for an LU factorization application under different parallelization and dynamic node allocation strategies

关键词： Computational modeling Concurrent computing Predictive models Resource management Application software Hardware Runtime Computer simulation Flow graphs Computer applications

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An overview of the ECO project 06

An overview of the ECO project

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International symposium on parallel and distributed processing (IPDPS)

作者： J. Chame Chun Chen P. Diniz M. Hall Yoon-Ju Lee R.F. Lucas Information Sciences Institute University of Southern California Marina del Rey CA USA

ISBN: (纸本)9781424400546

In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in high performance. Our approach combines compiler models and heuristics with guided empirical search to take advantage of their complementary strengths. The models and heuristics limit the search to a small number of candidate implementations, and the empirical results provide the most accurate information to the compiler to select among candidates and tune optimization parameter values. The overall approach can be employed to alleviate some of the performance problems that lead to inefficiencies in key applications today: register pressure, cache conflict misses, and the trade-off between synchronization, parallelism and locality in SMPs. The main focus of the paper is an algorithm for simultaneously optimizing across multiple levels of the memory hierarchy for dense-matrix computations. We have developed an initial compiler implementation, and present automatically-generated results on matrix multiply. Results on two architectures, SGI R10000 and Sun UltraSparc IIe, outperform the native compiler, and either outperform or achieve comparable performance as the ATLAS self-tuning library and the hand-tuned vendor BLAS library. This paper describes other components of the ECO system, including supporting tools and experiments with programmer-guided performance tuning. This approach has provided a foundation for a general framework for systematic optimization of domain-specific applications. Specifically, we are developing an optimization system for signal and image processing that exploits signal properties, and we are using machine learning and a knowledge-rich representation can be exploited to optimize molecular dynamics simulation

关键词： Tuning Libraries Signal processing Programming profession Optimizing compilers Registers parallel processing Focusing Computer architecture Sun

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