The performance and energy costs of coordinating and performing data movement have led to proposals adding compute units and/or specialized access units to the memory hierarchy. However, current on-chip offload models...
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ISBN:
(纸本)9781665462723
The performance and energy costs of coordinating and performing data movement have led to proposals adding compute units and/or specialized access units to the memory hierarchy. However, current on-chip offload models are restricted to fixed compute and access pattern types, which limits software-driven optimizations and the applicability of such an offload interface to heterogeneous accelerator resources. This paper presents a computation offload interface for multi-core systems augmented with distributed on-chip accelerators. With energy-efficiency as the primary goal, we define mechanisms to identify offload partitioning, create a low-overhead execution model to sequence these fine-grained operations, and evaluate a set of workloads to identify the complexity needed to achieve distributed near-data *** demonstrate that our model and interface, combining features of dataflow in parallel with near-data processing engines, can be profitably applied to memory hierarchies augmented with either specialized compute substrates or lightweight near-memory cores. We differentiate the benefits stemming from each of elevating data access semantics, near-data computation, inter-accelerator coordination, and compute/access logic specialization. Experimental results indicate a geometric mean (energy efficiency improvement; speedup; data movement reduction) of (3.3; 1.59; 2.4)×, (2.46; 1.43; 3.5)× and (1.46; 1.65; 1.48)× compared to an out-of-order processor, monolithic accelerator with centralized accesses and monolithic accelerator with decentralized accesses, respectively. Evaluating both lightweight core and CGRA fabric implementations highlights model flexibility and quantifies the benefits of compute specialization for energy efficiency and speedup at 1.23× and 1.43×, respectively.
Recent advances in hardware technologies raise new opportunities for architecting storage systems to exploit emerging NVRAM memory devices, fast remote-memory RDMA networking, and large numbers of processor cores. In ...
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In this paper, we describe and evaluate an extension of the CHAMELEON library to operate with hierarchical matrices (H-Matrices) and hierarchical arithmetic (H-Arithmetic), producing efficient solvers for linear syste...
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The GraphBLAS are building blocks for expressing graph algorithms in terms of linear algebra. Currently, the GraphBLAS are defined as a C API. Implementations of the GraphBLAS have exposed limitations in expressivenes...
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Welcome to the NSF/TCPP Workshop on parallel and distributed Computing Education (EduPar-20) proceedings. The EduPar-20 workshop, held in conjunction with the ieee International parallel and Computing symposium (IPDPS...
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ISBN:
(数字)9781728174457
ISBN:
(纸本)9781728174570
Welcome to the NSF/TCPP Workshop on parallel and distributed Computing Education (EduPar-20) proceedings. The EduPar-20 workshop, held in conjunction with the ieee International parallel and Computing symposium (IPDPS), is devoted to the development and assessment of educational and curricular innovations and resources for undergraduate and graduate education in parallel and distributed Computing (PDC). EduPar brings together individuals from academia, industry, and other educational and research institutes to explore new ideas, challenges, and experiences related to PDC pedagogy and curricula. The workshop is designed in coordination with the ieee TCPP curriculum initiative on parallel and distributed computing (http://***/~tcpp/curriculum) for computer science and computer engineering undergraduates, and is supported by the NSF and the NSF-supported Center for parallel and distributed Computing Curriculum Development and Educational Resources (CDER).
These are the proceedings of the “29th Heterogeneity in Computing Workshop,” also known as HCW 2020. A few years ago, the title of the workshop was changed from the original title of “Heterogeneous Computing Works...
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ISBN:
(数字)9781728174457
ISBN:
(纸本)9781728174570
These are the proceedings of the “29th Heterogeneity in Computing Workshop,” also known as HCW 2020. A few years ago, the title of the workshop was changed from the original title of “Heterogeneous Computing Workshop” to reflect the breadth of the impact of heterogeneity, as well as to stress that the focus of the workshop is on the management and exploitation of heterogeneity. All of this is, of course, taken in the context of the parent conference, the International parallel and distributedprocessingsymposium (IPDPS), and so explores heterogeneity in parallel and distributed computing systems.
This paper addresses the questions of high-level system modelling using heterogeneous multi-tool modelling environment on parallel multi-core processing systems for simulation acceleration. The modelling technique has...
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This paper addresses the questions of high-level system modelling using heterogeneous multi-tool modelling environment on parallel multi-core processing systems for simulation acceleration. The modelling technique has been applied for high-level validation of a high-precision Indoor Positioning System for Motion Analysis (IPS-MA) developed in the Central Institute Electronic Systems (ZEA-2) of the Research Center Juelich GmbH. The heterogeneous modelling environment has been built using an implementation-level model designed in Matlab Simulink, a verification model for describing the system environment using Modelica language, and Julia language for automatic generation of binding modelling environment and parallelizing the simulation of the overall model. The approach showed a good flexibility in system description and verification in the multi-instrument modelling environment and a good performance gain due to simulation parallelism.
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
ISBN:
(数字)9781728174457
ISBN:
(纸本)9781728174570
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
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