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Toward using higher-level abstractions to teach parallel computing

Toward using higher-level abstractions to teach parallel com...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Ferner, Clayton Wilkinson, Barry Heath, Barbara University of North Carolina Wilmington 601 S. College Rd. Wilmington NC 28403 United States University of North Carolina Charlotte 9201 University City Blvd. Charlotte NC 28223 United States East Main Evaluation and Consulting LLC P.O. Box 12343 Wilmington NC 28405 United States

ISBN: (纸本)9780769549798

We have developed two new approaches to teaching parallel computing to undergraduates using higher level tools that lead to ease of programming, good software design, and scalable programs. The first approach uses a new software environment that creates a higher level of abstraction for parallel and distributed programming based upon a pattern programming approach. The second approach uses compiler directives to describe how a program should be parallelized. We have studied whether using the above tools better helps the students grasp the concepts of parallel computing across the two campuses of the University of North Carolina Wilmington and the University of North Carolina Charlotte using a televideo network. We also taught MPI and OpenMP in the traditional fashion with which we could ask the students to compare and contrast the approaches. An external evaluator conducted three surveys during the semester and analyzed the data. In this paper, we discuss the techniques we used, the assignments we gave the students, and the results of what we learned. © 2013 ieee.

关键词： Students

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TSHMEM: Shared-memory parallel computing on tilera many-core processors

TSHMEM: Shared-memory parallel computing on tilera many-core...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Lam, Bryant C. George, Alan D. Lam, Herman NSF Center for High-Performance Reconfigurable Computing Department of Electrical and Computer Engineering University of Florida Gainesville FL 32611-6200 United States

ISBN: (纸本)9780769549798

With many-core processor architectures emerging, concerns arise regarding the productivity of numerous parallel programming tools, models, and languages as developers from a broad spectrum of science domains struggle to maximize performance and maintain correctness of their applications. Fortunately, a partitioned global address space (PGAS) programming model has demonstrated realizable performance and productivity potential for large parallel computing systems with distributed-memory architectures. One such PGAS approach is SHMEM, a lightweight, shared-memory programming library. Renewed interest for SHMEM has developed around Oppenheim, a recent community-led effort to produce a standardized specification for the SHMEM library amidst incompatible commercial implementations. This paper presents and evaluates the design of TSHMEM (short for TileSHMEM), a new OpenSHMEM library for the Tilera TILE-Gx8036 and TILEPro64 many-core processors. TSHMEM is built atop Tilera-provided libraries with key emphasis upon realizable performance with those libraries, demonstrated through micro benchmarking. Furthermore, SHMEM application portability is illustrated with two case studies. TSHMEM successfully delivers high performance with ease of programmability and portability for SHMEM applications on TILE-Gx and TILEPro architectures. © 2013 ieee.

关键词： parallel programming

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Virtual SoC: A full-system simulation environment for massively parallel heterogeneous system-on-chip

Virtual SoC: A full-system simulation environment for massiv...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Bortolotti, Daniele Pinto, Christian Marongiu, Andrea Ruggiero, Martino Benini, Luca DEI-University of Bologna Viale Risorgimento 2 40136 Bologna Italy

ISBN: (纸本)9780769549798

Driven by flexibility, performance and cost constraints of demanding modern applications, heterogeneous System-on-Chip (SoC) is the dominant design paradigm in the embedded system computing domain. SoC architecture and heterogeneity clearly provide a wider power/performance scaling, combining high performance and power efficient general-purpose cores along with massively parallel many-core-based accelerators. Besides the complex hardware, generally these kinds of platforms host also an advanced software ecosystem, composed by an operating system, several communication protocol stacks, and various computational demanding user applications. The necessity to efficiently cope with the hugeHW/SW design space provided by this scenario makes clearly full-system simulator one of the most important design tools. We present in this paper a new emulation framework, called Virtual SoC, targeting the full-system simulation of massively parallel heterogeneous SoCs. © 2013 ieee.

关键词： System-on-chip

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HPC system software for regular and irregular parallel applications

HPC system software for regular and irregular parallel appli...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Morari, Alessandro Valero, Mateo Barcelona Supercomputing Center Barcelona Spain Universitat Politecnica de Catalunya Barcelona Spain

ISBN: (纸本)9780769549798

The upcoming generation of system software for High Performance Computing is expected to provide a richer set of functionalities without compromising application performance. This Ph.D. thesis addresses the problem of designing scalable system software for both regular and irregular applications. The contributions are two-fold. First, we evaluate the drawbacks of current HPC system software for regular applications. We describe a methodology to precisely measure jitter on a general-purpose OS. Considering a lightweight operating system (IBM CNK), we analyze the overhead of adding support for a missing feature such as dynamic memory management. Second, we focus on irregular applications and build a specialized runtime system to enhance this kind of applications on common HPC flop intensive systems. The proposed runtime system provides a global address space abstraction of a distributed memory machine combined with a transparent fork/join execution model and it also includes lightweight multithreading and network message aggregation. © 2013 ieee.

关键词： Jitter

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Lega SCi: Legacy system C model integration into parallel systemc simulators

Lega SCi: Legacy system C model integration into parallel sy...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Schumacher, Christoph Weinstock, Jan Henrik Leupers, Rainer Ascheid, Gerd Tosoratto, Laura Lonardo, Alessandro Petras, Dietmar Grotker, Thorsten Institute for Communication Technologies and Embedded Systems RWTH Aachen University Germany Istituto Nazionale di Fisica Nucleare Sezione di Roma Rome Italy Synopsys Inc. Aachen Germany

ISBN: (纸本)9780769549798

Virtual prototyping of parallel and embedded systems increases insight into existing computer systems. It further allows to explore properties of new systems already during their specification phase. Virtual prototypes of such systems benefit from parallel simulation techniques due to the increased simulation speed. One common problem full system simulator implementers face is the revision and integration of legacy models coded without thread-safety and deterministic behavior in mind. To lessen this burden, this paper presents a methodology to integrate unmodified SystemC legacy models into parallel SystemC simulators. Using the proposed technique, the embedded platform simulator of the EU FP7 project EURETILE, which inherited a number of legacy models from its predecessor project SHAPES, has been transformed into a parallel simulation platform, demonstrating speed-ups of up to 3.36 on four simulation host cores. © 2013 ieee.

关键词： Simulators

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Network delay-Aware load balancing in selfish and cooperative distributed systems

Network delay-Aware load balancing in selfish and cooperativ...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Skowron, Piotr Rzadca, Krzysztof Faculty of Mathematics Informatics and Mechanics University of Warsaw Warsaw Poland

ISBN: (纸本)9780769549798

We consider a geographically distributed request processing system composed of various organizations and their servers connected by the Internet. The latency a user observes is a sum of communication delays and the time needed to handle the request on a server. The handling time depends on the server congestion, i.e. the total number of requests a server must handle. We analyze the problem of balancing the load in a network of servers in order to minimize the total observed latency. We consider both cooperative and selfish organizations (each organization aiming to minimize the latency of the locally-produced requests). The problem can be generalized to the task scheduling in a distributed cloud;or to content delivery in an organizationally-distributed CDNs. In a cooperative network, we show that the problem is polynomially solvable. We also present a distributed algorithm iteratively balancing the load. We show how to estimate the distance between the current solution and the optimum based on the amount of load exchanged by the algorithm. During the experimental evaluation, we show that the distributed algorithm is efficient, therefore it can be used in networks with dynamically changing loads. In a network of selfish organizations, we prove that the price of anarchy (the worst-case loss of performance due to selfishness) is low when the network is homogeneous and the servers are loaded (the request handling time is high compared to the communication delay). After relaxing these assumptions, we assess the loss of performance caused by the selfishness experimentally, showing that it remains low. Our results indicate that a set of servers handling requests, connected in a heterogeneous network, can be efficiently managed by a distributed algorithm. Additionally, even if the network is organizationally distributed, with individual organizations optimizing performance of their requests, the network remains efficient. © 2013 ieee.

关键词： Heterogeneous networks

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parallel algorithms for graph optimization using tree decompositions

Parallel algorithms for graph optimization using tree decomp...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Sullivan, Blair D. Weerapurage, Dinesh Groer, Chris Oak Ridge National Laboratory P.O. Box 2008 Oak Ridge TN 37831-6015 United States Link Analytics 1050 Crown Pointe Pkwy Atlanta GA 30338 United States

ISBN: (纸本)9780769549798

Although many NP-hard graph optimization problems can be solved in polynomial time on graphs of bounded tree-width, the adoption of these techniques into mainstream scientific computation has been limited due to the high memory requirements of the dynamic programming tables and excessive runtimes of sequential implementations. This work addresses both challenges by proposing a set of new parallel algorithms for all steps of a tree decomposition-based approach to solve the maximum weighted independent set problem. A hybrid OpenMP/MPI implementation includes a highly scalable parallel dynamic programming algorithm leveraging the MADNESS task based runtime, and computational results demonstrate scaling. This work enables a significant expansion of the scale of graphs on which exact solutions to maximum weighted independent set can be obtained, and forms a framework for solving additional graph optimization problems with similar techniques. © 2013 ieee.

关键词： Trees (mathematics)

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parallel macro pipelining on the intel SCC many-core computer

Parallel macro pipelining on the intel SCC many-core compute...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Suss, Tim Schoenrock, Andrew Meisner, Sebastian Plessl, Christian Johannes Gutenberg-University Mainz Zentrum fur Datenverarbeitung Mainz Germany Carleton University School of Computer Science Ottawa Canada University of Paderborn Paderborn Center for Parallel Computing Paderborn Germany

ISBN: (纸本)9780769549798

In this paper we present how Intel's Single-Chip-Cloud processor behaves for parallel macro pipeline applications. Subsets of the SCC's available cores can be arranged as a pipeline where each core processes one stage of the overall workload. Each of the independent cores processes a small part of a larger task and feeds the following core with new data after it finishes its work. Our case-study is a parallel rendering system which renders successive images and applies different filters on them. On normal graphics adapters this is usually done in multiple cycles, we do this in a single pipeline pass. We show that we can achieve a significant speedup by using multiple parallel pipelines on the SCC. We show that we can further improve performance by using SCC's controlling PC in conjunction with the SCC. We also identify aspects of the SCC that hinder the overall performance, mainly the lack of local memory banks for each core on the SCC. The results presented in this paper are not limited to only image processing, but users could expect similar experiences where macro pipelining is used in other applications on the SCC. © 2013 ieee.

关键词： Pipelines

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Proper orthogonal decomposition based parallel compression for visualizing big data on the K computer

Proper orthogonal decomposition based parallel compression f...

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2013 3rd ieee symposium on Large-Scale Data Analysis and Visualization, LDAV 2013

作者： Bi, Chongke Ono, Kenji Ma, Kwan-Liu Wu, Haiyuan Imamura, Toshiyuki RIKEN Japan University of California Davis United States Wakayama University Japan

ISBN: (纸本)9781479916597

The development of supercomputers has greatly help us to carry on large-scale computing for dealing with various problems through simulating and analyzing them. Visualization is an indispensable tool to understand the properties of the data from supercomputers. Especially, interactive visualization can help us to analyze data from various viewpoints and even to find out some local small but important features. However, it is still difficult to interactively visualize such kind of big data directly due to the slow file I/O problem and the limitation of memory size. For resolving these problems, we proposed a parallel compression method to reduce the data size with low computational cost. Furthermore, the fast linear decompression process is another merit for interactive visualization. Our method uses proper orthogonal decomposition (POD) to compress data because it can effectively extract important features from the data and the resulting compressed data can also be linearly decompressed. Our implementation achieves high parallel efficiency with a binary load-distributed approach, which is similar to the binary-swap image composition used in parallel volume rendering [2]. This approach allows us to effectively utilize all the processing nodes and reduce the interprocessor communication cost throughout the parallel compression calculations. Our test results on the K computer demonstrate superior performance of our design and implementation. © 2013 ieee.

关键词： Supercomputers

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HadoopCL: MapReduce on distributed heterogeneous platforms through seamless integration of hadoop and OpenCL

HadoopCL: MapReduce on distributed heterogeneous platforms t...

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2013 ieee 37th Annual Computer Software and Applications Conference, COMPSAC 2013

作者： Grossman, Max Breternitz, Mauricio Sarkar, Vivek Department of Computer Science Rice University United States AMD United States

ISBN: (纸本)9780769549798

As the scale of high performance computing systems grows, three main challenges arise: the programmability, reliability, and energy efficiency of those systems. Accomplishing all three without sacrificing performance requires a rethinking of legacy distributed programming models and homogeneous clusters. In this work, we integrate Hadoop MapReduce with OpenCL to enable the use of heterogeneous processors in a distributed system. We do this by exploiting the implicit data parallelism of mappers and reducers in a MapReduce system. Combining Hadoop and OpenCL provides 1) an easy-to-learn and flexible application programming interface in a high level and popular programming language, 2) the reliability guarantees and distributed file system of Hadoop, and 3) the low power consumption and performance acceleration of heterogeneous processors. This paper presents HadoopCL: an extension to Hadoop which supports execution of user-written Java kernels on heterogeneous devices, optimizes communication through asynchronous transfers and dedicated I/O threads, automatically generates OpenCL kernels from Java byte code using the open source tool APARAPI, and achieves nearly 3x overall speedup and better than 55x speedup of the computational sections for example MapReduce applications, relative to Hadoop. © 2013 ieee.

关键词： MapReduce

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