This paper describes issues concerning the design of an optimistic parallel discrete event simulation system that executes in environments that impose real-time constraints on the simulator's execution. Two key pr...
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ISBN:
(纸本)9781565550278
This paper describes issues concerning the design of an optimistic parallel discrete event simulation system that executes in environments that impose real-time constraints on the simulator's execution. Two key problems must be addressed by such a system. First the timing characteristics of the parallel simulator must be sufficiently predictable to allow one to guarantee that real-time deadlines for completing simulation computations will be met. Second, the optimistic computation must be able to interact with its surrounding environment with as little latency as possible, necessitating rapid commitment of I/O *** address the first question, we show that optimistic simulators that never send incorrect messages (sometimes called “aggressive-no-risk” simulators) provide sufficient predictability to allow traditional schedulability analysis techniques commonly used in real-time systems to be applied. We show that incremental state saving techniques introduce sufficient unpredictability that they are not well-suited for real-time environments. We observe that the traditional “lowest timestamp first” scheduling policy used in many optimistic parallelsimulation systems is an optimal (in the real-time sense) scheduling algorithm when event timestamps and real-time deadlines are the same. Finally, to address the question for rapid commitment of I/O operations, we utilize a continuous GVT computation scheme for shared-memory multiprocessors where a new value of GVT is computed after processing each event in the *** ideas are incorporated in a parallel, optimistic, real-time simulation system called PORTS. Initial performance measurements of the shared-memory based PORTS system executing on a Kendall Square Research multiprocessor are presented. Initial performance results are encouraging, demonstrating that PORTS achieves performance approaching that of a conventional Time Warp system for the benchmark programs that were tested.
We present, in this paper, a hybrid algorithm which makes use of Time Warp between clusters of LPs and a sequential algorithm within the cluster. Time Warp is, of course, traditionally implemented between individual L...
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We present, in this paper, a hybrid algorithm which makes use of Time Warp between clusters of LPs and a sequential algorithm within the cluster. Time Warp is, of course, traditionally implemented between individual LPs. The algorithm was implemented in a digital logic simulator, and its performance compared to that of Time Warp. Resting upon this platform we develop a family of three checkpointing algorithms, each of which occupies a different point in the spectrum of possible trade-offs between memory usage and execution time. The algorithms were implemented on several digital logic circuits and their speed, number of states saved and maximal memory consumption were compared to those of Time Warp. One of the algorithms saved between 35 and 50% of the maximal memory consumed by Time Warp (depending upon the number of processors used), while the other two decreased the maximal usage up to 30%. The latter two algorithms exhibited a speed comparable to Time Warp, while the first algorithm was 30-60% slower. These algorithms are also simpler to implement than optimal checkpointing algorithms.
The efficient processing of tree-based multiple-task jobs arriving in batches to parallel and distributed systems is presented. This type of processing can be found in such application fields as, for example, automati...
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An approach to flexible and efficient data parallelsimulation of neural networks on large scale M1MD-machines is presented. We regard the exploitation of the inherent parallelism of neural network models as necessary...
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This paper describes design issues and preliminary considerational factors for highly parallel commercial computer design. The design issues described in this paper include application area analysis, scalability, avai...
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We discuss a novel technique for improving the dependability of parallel programs executing on a MIMD shared memory architecture. The idea is to empower certain tasks of each application program to carry out failure d...
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This paper describes a modeling project which was established to support the design of a distributed controller system. An anthropomorphic robot hand is the target system. Stochastic Petri net models for different com...
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Conformance testing of communication protocols has recently become a major issue in the context ofOSI-based standardization of protocols. The aim of conformance testing is to assure that a protocol fulfills an OSI spe...
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In a distributed real-time system, tolerance to faults on processing nodes in the system is achieved by means of redundant nodes and a fault-tolerant scheduling algorithm. Since redundant nodes increase total failure ...
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This paper discusses the algorithms for numerical simulation of semuconductor devices (in particular using quasi-hydrodynamic model) on multiprocessor computer systems with distributed memory. parallel implementation ...
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